SI9130_11 Datasheet, PDF (13/15 Pages) Vishay Siliconix – Pin-Programmable Dual Controller - Portable PCs

DESIGN CONSIDERATIONS
Inductor Design
Three specifications are required for inductor design:
inductance (L), peak inductor current (I_LPEAK), and coil
resistance (R_L). The equation for computing inductance is:
L
V_OUT V_IN(MAX)- V_OUT
V_IN(MAX) ^(f) I_OUT ^(LIR)
Where: V_OUT = Output voltage (3.3 V or 5 V);
V_IN(MAX) = Maximum input voltage (V);
f = Switching frequency, normally 300 kHz;
I_OUT = Maximum dc load current (A);
LIR = Ratio of inductor peak-to-peak ac current to average dc
load current, typically 0.3.
When LIR is higher, smaller inductance values are
acceptable, at the expense of increased ripple and higher
losses.
The peak inductor current (I_LPEAK) is equal to the steady-
state load current (I_OUT) plus one half of the peak-to-peak ac
current (I_LPP). Typically, a designer will select the ac inductor
current to be 30 % of the steady-state current, which gives
I_LPEAK equal to 1.15 times I_OUT.
The equation for computing peak inductor current is:
I_LPEAK
I_OUT + ^{VOUT VIN(MAX) - VOUT}
(2)(f)(L) V_IN(MAX)
OUTPUT CAPACITORS
The output capacitors determine loop stability and ripple
voltage at the output. In order to maintain stability, minimum
capacitance and maximum ESR requirements must be met
according to the following equations:
C_F
and,
V_REF
V_OUT R_CS (2)(π)(GBWP)
ESR_CF
V_OUT R_CS
V_REF
Si9130
Vishay Siliconix
Where: C_F = Output filter capacitance (F)
V_REF = Reference voltage, 3.3 V;
V_OUT = Output voltage, 3.3 V or 5 V;
R_CS = Sense resistor ();
GBWP = Gain-bandwidth product, 60 kHz;
ESR_CF = Output filter capacitor ESR ().
Both minimum capacitance and maximum ESR
requirements must be met. In order to get the low ESR, a
capacitance value of two to three times greater than the
required minimum may be necessary.
The equation for output ripple in continuous current mode is:
V_OUT(RPL)
I_{LPP(MAX) x}
ESR_CF +
1
2 x f x CF
The equations for capacitive and resistive components of the
ripple in pulse-skipping mode are:
V_OUT(RPL)(C)
(4) 10^{- 4} (L)
x
R_CS2 C_F
1
V_OUT
+
1
V_IN - V_OUT
Volts
V_OUT(RPL)(R)
(0.02) ESR_CF
R_CS
Volts
The total ripple, V_OUT(RPL), can be approximated as follows:
if V_OUT(RPL)(R) < 0.5 V_OUT(RPL)(C),
then V_OUT(RPL) = V_OUT(RPL)(C),
otherwise, V_OUT(RPL) = 0.5 V_OUT(RPL)(C) +
V_OUT(RPL)(R).
Lower Voltage Input
The application circuit shown here can be easily modified to
work with 5.5 V to 12 V input voltages. Oscillation frequency
should be set at 200 kHz and increase the output
capacitance to 660 µF on the 5 V output to maintain stable
performance up to 2 A of load current. Operation on the
3.3 V supply will not be affected by this reduced input
voltage.
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Tech-
nology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability
data, see www.vishay.com/ppg?70190.
Document Number: 70190
www.vishay.com
S11-0975-Rev. G, 16-May-11
13
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000