SIP12108 Datasheet, PDF (12/18 Pages) Vishay Siliconix – Adjustable output voltage down to 0.6 V

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Pre-bias Startup
In case of pre-bias startup, output is monitored through V_FB
pin. If the sensed voltage on V_FB is higher than the internal
reference ramp value, control logic prevents HS and LS FET
from switching to avoid negative output voltage spike and
excessive current sinking through LS FET.
SiP12108, SiP12108A
Vishay Siliconix
Power Good (PGOOD)
SiP12108’s Power Good is an open-drain output. Pull
PGOOD pin high up to 5 V through a 10K resistor to use this
signal. Power Good window is shown in the below diagram.
If voltage level on V_FB pin is out of this window, PGOOD
signal is de-asserted by pulling down to GND.
VFB_Rising_Vth_OV
(Typ. = 0.725 V)
Vref (0.6 V)
V_FB
Pull-high
PGOOD
VFB_Falling_Vth_OV
(Typ. = 0.675 V)
VFB_Falling_Vth_UV
(Typ. = 0.525 V)
VFB_Rising_Vth_UV
(Typ. = 0.575 V)
Pull-low
Fig. 24 - PGOOD Window and Timing Diagram
DESIGN PROCEDURE
The design process of the SiP12108 is quite straight
forward. Only few passive components such as output
capacitors, inductor and R_on resistor need to be selected.
The following paragraph describes the selection procedure
for these peripheral components for a given operating
conditions.
In the next example the following definitions apply:
V_INmax.: the highest specified input voltage
V_INmin.: the minimum effective input voltage subject to
voltage drops due to connectors, fuses, switches,
and PCB traces
There are two values of load current to evaluate - continuous
load current and peak load current.
Continuous load current relates to thermal stress
considerations which drive the selection of the inductor and
input capacitors.
Peak load current determines instantaneous component
stresses and filtering requirements such as inductor
saturation, output capacitors, and design of the current limit
circuit.
The following specifications are used in this design:
• V_IN = 3.3 V ± 10 %
• V_OUT = 1.2 V ± 1 %
• F_SW = 1 MHz
• Load = 5 A maximum
Setting the Output Voltage
The output voltage is set by using a resistor divider on the
feedback (V_FB) pin. The V_FB pin is the negative input of the
internal error amplifier.
When in regulation the V_FB voltage is 0.6 V. The output
voltage V_O is set based on the following formula.
V_O = V_FB (1 + R1/R2)
where R1 and R2 are shown in figure 21.
Setting Switching Frequency
Selection of the switching frequency requires making a
trade-off between the size and cost of the external filter
components (inductor and output capacitor) and the power
conversion efficiency. The desired switching frequency,
1 MHz was chosen based on optimizing efficiency while
maintaining a small footprint and minimizing component
cost.
In order to set the design for 1 MHz switching frequency,
(R_ON) resistor which determines the on-time (indirectly
setting the frequency) needs to be calculated using the
following equation.
R_ON
=
----------¹-----------
F_SW x K
=
------------------------------¹--------------------------------
1 x 10⁶ x 10.45 x 10^-12

105
k
S13-2257-Rev. B, 11-Nov-13
12
Document Number: 62699
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