SIC530 Datasheet, PDF (11/17 Pages) Vishay Siliconix – 30 A VRPower Integrated Power Stage

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Step 5: Signal Routing
A_GND
A_GND
Step 7: Ground Connection
SiC530
Vishay Siliconix
AGND
V_SWH
P_GND
PGND
1. Route the PWM and ZCD_EN# signal traces out of the
top left corner next to pin 1.
2. The PWM signal is an important signal, both signal and
return traces should not cross any power nodes on any
layer.
3. It is best to “shield” these traces from power switching
nodes, e.g. V_SWH, with a GND island to improve signal
integrity.
4. GL (pin 19) has been connected with GL pad (pin 24)
internally.

Step 6: Adding Thermal Relief Vias
1. It is recommended to make a single connection between
A_GND and P_GND which can be made on the top layer.
2. It is recommended to make the entire first inner layer
(below top layer) the ground plane and separate them
into A_GND and P_GND planes.
3. These ground planes provide shielding between noise
sources on top layer and signal traces on bottom layer.
AGND
VIN
PGND
V_SWH
V_IN Plane
P_GND Plane
1. Thermal relief vias can be added on the V_IN and A_GND
pads to utilize inner layers for high-current and thermal
dissipation.
2. To achieve better thermal performance, additional vias
can be placed on V_IN plane and P_GND plane.
3. V_SWH pad is a noise source, it is not recommended to
place vias on this pad.
4. 8 mil vias for pads and 10 mils vias for planes are the
optimal via sizes. Vias on pad may drain solder during
assembly and cause assembly issues. Consult with the
assembly house for guidelines.
S15-2523-Rev. B, 02-Nov-15
11
Document Number: 62940
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