SIC417 Datasheet, PDF (10/21 Pages) Vishay Siliconix – microBUCK SiC417 10-A, 28-V Integrated Buck Regulator with Programmable LDO

SiC417
Vishay Siliconix
VOUT drifts up to due to leakage
current flowing into COUT
Smart power save
threshold (550 mV)
FB
threshold
DH and DL off
VOUT discharges via inductor
and low-side MOSFET
Normal VOUT ripple
High-side
drive (DH)
Single DH on-time pulse
after DL turn-off
Low-side
drive (DL)
DL turns on when smart
PSAVE threshold is reached
DL turns off FB
threshold is reached
Normal DL pulse after DH
on-time pulse
Figure 7 - Smart Power-Save
Current Limit Protection
The SiC417 features programmable current limit capability,
which is accomplished by using the R_DS(ON) of the lower
MOSFET for current sensing. The current limit is set by R_ILIM
resistor. The R_ILIM resistor connects from the I_LIM pin to the
LX pin which is also the drain of the low-side MOSFET.
When the low-side MOSFET is on, an internal ~ 10 µA
current flows from the I_LIM pin and the R_ILIM resistor, creating
a voltage drop across the resistor. While the low-side
MOSFET is on, the inductor current flows through it and
creates a voltage across the R_DS(ON). The voltage across the
MOSFET is negative with respect to ground.
If this MOSFET voltage drop exceeds the voltage across
R_ILIM, the voltage at the I_LIM pin will be negative and current
limit will activate. The current limit then keeps the low-side
MOSFET on and will not allow another high-side on-time,
until the current in the low-side MOSFET reduces enough to
bring the I_LIM voltage back up to zero. This method regulates
the inductor valley current at the level shown by I_LIM in
figure 8.
IPEAK
ILOAD
ILIM
Time
Figure 8 - Valley Current Limit
Setting the valley current limit to 10 A results in a 10 A peak
inductor current plus peak ripple current. In this situation, the
average (load) current through the inductor is 10 A plus
one-half the peak-to-peak ripple current.
The internal 10 µA current source is temperature
compensated at 4100 ppm in order to provide tracking with
the R_DS(ON). The R_ILIM value is calculated by the following
equation.
R_ILIM = 735 x I_LIM
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Note that because the low-side MOSFET with low R_DS(ON) is
used for current sensing, the PCB layout, solder
connections, and PCB connection to the LX node must be
done carefully to obtain good results. Refer to the layout
guidelines for information.
Soft-Start of PWM Regulator
Soft-start is achieved in the PWM regulator by using an
internal voltage ramp as the reference for the FB
Comparator. The voltage ramp is generated using an internal
charge pump which drives the reference from zero to 500 mV
in ~ 1.2 mV increments, using an internal ~ 500 kHz
oscillator. When the ramp voltage reaches 500 mV, the ramp
is ignored and the FB comparator switches over to a fixed
500 mV threshold. During soft-start the output voltage tracks
the internal ramp, which limits the start-up inrush current and
provides a controlled softstart profile for a wide range of
applications. Typical softstart ramp time is 850 µs. During
soft-start the regulator turns off the low-side MOSFET on any
cycle if the inductor current falls to zero. This prevents
negative inductor current, allowing the device to start into a
pre-biased output.
Power Good Output
The power good (P_GOOD) output is an open-drain output
which requires a pull-up resistor. When the output voltage is
10 % below the nominal voltage, P_GOOD is pulled low. It is
held low until the output voltage returns above - 8 % of
nominal. P_GOOD is held low during start-up and will not be
allowed to transition high until soft-start is completed (when
V_FB reaches 500 mV) and typically 2 ms has passed.
P_GOOD will transition low if the V_FB pin exceeds + 20 % of
nominal, which is also the over-voltage shutdown threshold
(600 mV). P_GOOD also pulls low if the EN/PSV pin is low
when V5V is present.
Output Over-Voltage Protection
Over-voltage protection becomes active as soon as the
device is enabled. The threshold is set at 500 mV + 20 %
(600 mV). When V_FB exceeds the OVP threshold, DL latches
high and the low-side MOSFET is turned on. DL remains
high and the controller remains off , until the EN/PSV input is
toggled or V5V is cycled. There is a 5 µs delay built into the
OVP detector to prevent false transitions. P_GOOD is also low
after an OVP event.
Output Under-Voltage Protection
When V_FB falls 25 % below its nominal voltage (falls to
375 mV) for eight consecutive clock cycles, the switcher is
shut off and the DH and DL drives are pulled low to tristate
the MOSFETs. The controller stays off until EN/PSV is
toggled or V5V is cycled.
V5V UVLO, and POR
Under-voltage lock-out (UVLO) circuitry inhibits switching
and tri-states the DH/DL drivers until V5V rises above 3.9 V.
An internal Power-On Reset (POR) occurs when V5V
exceeds 3.9 V, which resets the fault latch and soft-start
Document Number: 69062
S10-1367-Rev. D, 14-Jun-10