VSM85 Datasheet, PDF (1/2 Pages) Vishay Siliconix – Bulk Metal® Foil Technology Surface Mount Hermetic Resistor Networks In Leadless Chip Carrier (LCC) Configuration

VSM85, 86, 87, 88, 89
Vishay Foil Resistors
Bulk Metal^® Foil Technology
Surface Mount Hermetic Resistor Networks In
Leadless Chip Carrier (LCC) Configuration
Product may not
be to scale
Vishay Model VSM networks incorporate all the performance
features of Vishay Bulk Metal^® Foil technology in a product
ready for surface mounting. The multi-terminal ceramic LCC
has gold plated terminals which wrap around from the side of the
package to the underside for either socket or surface mounting.
See data sheet “7 Technical Reasons to Specify Bulk Metal^®
Foil Resistor Networks.”
ORDERING INFORMATION - VSM85, VSM86,
VSM87, VSM88 OR VSM89 NETWORKS
Networks are built to your requirements. Send your schematic
and electrical requirements to the Applications Engineering
Department. (See data sheet “Network Worksheet:.) A unique
part number will be assigned which defines all aspects of your
network.
FIGURE 1 - PACKAGE SIZES AND CHARACTERISTICS
L
0.100
(2.45) ^REFERENCE
NOTE:
1. These networks utilize Vishay Bulk Metal^® Foil
0.025
(0.64)
TYPICAL
resistor chips V5X5 and V15X5 or VTF15X5 Thin
Film chips.
0.008 REFERENCE
W
(0.20) TYPICAL
2. The V5X5 and V15X5 chips have maximum
0.050
(1.27)
TYPICAL
0.025
(0.64)
0.045
(1.14)
H
0.050
(00..03102)^R
REF
(1.27)
TYPICAL
TYPICAL
resistance values of 10K and 33K respectively in
Bulk Metal^® Foil and 500K in VTF15X5 Thin Film
chips.
3. The V5X5 and V15X5 chip(s) can be intermixed
in a package.
VISHAY
MODEL
VSM85
VSM86
VSM87
VSM88
VSM89
NO. OF
PINS
16
20
24
28
32
MAXIMUM DIMENSIONS in Inches (mm)
L
W
H
LL
0.295 (7.493) 0.360 (9.144) 0.090 (2.286)
N/A
0.360 (9.144) 0.360 (9.144) 0.090 (2.286)
N/A
0.345 (8.763) 0.345 (8.763) 0.090 (2.286)
N/A
0.460 (11.684) 0.460 (11.684) 0.090 (2.286)
N/A
0.460 (11.684) 0.560 (14.224) 0.090 (2.286)
N/A
CHIP CAPACITY _{MAXIMUM POWER RATING}
V5X5
V15X5
(WATTS) @ +70°C
12
4
0.4
16
4
0.6
16
5
0.6
25
10
1.0
35
14
1.4
FIGURE 2 - SAMPLE CIRCUIT DESIGN AND CHIP LAYOUT
10 9 8 7
11
6
R6
12
R7
5
NOTE:
Usable area is represented by the dotted lines— a rectangle 0.150"
x 0.200". Illustrations not to scale. Chips shown undersize for
clarity. Drawing view is from the top looking down into the package.
R9 R8
R10
R1
R3
R2
13
R4
4
R5
13
R1
4
R2
16
R4
R3
1
R5
9
R6
8
R7
12
R9
R8
5
R10
14
3
15 16 1 2
SALES
• ISRAEL: [e-mail] • FRANCE/SWITZERLAND/SOUTHERN EUROPE: [e-mail] • AMERICAS: [e-mail]
• ASIA/JAPAN: [e-mail] • UK/HOLLAND/SCANDINAVIA: [e-mail] • GERMANY/CZECH REPUBLIC/AUSTRIA: [e-mail]
www.vishay.com
52
For technical questions in the Americas, contact [e-mail]
Document Number: 63028
For technical questions in Asia/Japan/Europe/Africa/Israel, contact [e-mail] Revision 08-Mar-05