TLV2544Q Datasheet, PDF (1/37 Pages) Texas Instruments – 3-V TO 5.5-V, 12-BIT, 200-KSPS, 4-/8-CHANNEL, LOW-POWER SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER-DOWN

TLV2544Q, TLV2548Q, TLV2548M
3-V TO 5.5-V, 12-BIT, 200-KSPS, 4-/8-CHANNEL, LOW-POWER
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER-DOWN
SGLS119C – FEBRUARY 2002 – REVISED OCTOBER 2002
D Maximum Throughput 200-KSPS
D Built-In Reference, Conversion Clock and
8× FIFO
D Differential/Integral Nonlinearity Error:
±1.2 LSB at –55°C to 125°C
D Signal-to-Noise and Distortion Ratio:
65 dB, f_i = 12-kHz at –55°C to 125°C
D Spurious Free Dynamic Range: 75 dB,
f_i = 12- kHz
D SPI/DSP-Compatible Serial Interfaces With
SCLK up to 20-MHz
D Single Wide Range Supply 3 Vdc to
5.5 Vdc
D Analog Input Range 0-V to Supply Voltage
With 500 kHz BW
D Hardware Controlled and Programmable
Sampling Period
D Low Operating Current (1-mA at 3.3-V,
2-mA at 5.5-V With External Ref, 1.7-mA at
3.3-V, 2.4-mA at 5.5-V With Internal Ref)
D Power Down: Software/Hardware
Power-Down Mode (1 µA Typ, Ext Ref),
Autopower-Down Mode (1 µA Typ, Ext Ref)
D Programmable Auto-Channel Sweep
D Available in Q-Temp Automotive
High Reliability Automotive Applications
Configuration Control/Print Support
Qualification to Automotive Standards
TLV2548Q . . . DW PACKAGE
(TOP VIEW)
TLV2544Q . . . D PACKAGE
(TOP VIEW)
TLV2548M . . . FK PACKAGE
(TOP VIEW)
SDO 1
SDI 2
SCLK 3
EOC/(INT) 4
V_CC 5
A0 6
A1 7
A2 8
A3 9
A4 ¹⁰
20 CS
19 REFP
18 REFM
17 FS
16 PWDN
15 GND
14 CSTART
13 A7
12 A6
11 _A5
SDO 1
SDI 2
SCLK 3
EOC/(INT) 4
V_CC 5
A0 6
A1 7
A2 8
16 CS
15 REFP
14 REFM
13 FS
12 PWDN
11 GND
10 CSTART
9 A3
3 2 1 20 19
EOC/(INT) ₄
18 ^REFM
V_{CC 5}
17 ^FS
A0 ₆
16 ^PWDN
A1 ₇
15 ^GND
A2 ₈
14 ^CSTART
9 10 11 12 13
description
The TLV2544Q, TLV2548Q, and TLV2548M are a family of high performance, 12-bit low power, 3.5 µs, CMOS
analog-to-digital converters (ADC) which operate from a single 3-V to 5.5-V power supply. These devices have
three digital inputs and a 3-state output [chip select (CS), serial input-output clock (SCLK), serial data input
(SDI), and serial data output (SDO)] that provide a direct 4-wire interface to the serial port of most popular host
microprocessors (SPI interface). When interfaced with a DSP, a frame sync (FS) signal is used to indicate the
start of a serial data frame.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright  2002, Texas Instruments Incorporated
1