SN54BCT573_08 Datasheet, PDF (1/16 Pages) Texas Instruments – OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

D Operating Voltage Range of 4.5 V to 5.5 V
D State-of-the-Art BiCMOS Design
Significantly Reduces I_CCZ
D Full Parallel Access for Loading
SN54BCT573 . . . J OR W PACKAGE
SN74BCT573 . . . DW, N, OR NS PACKAGE
(TOP VIEW)
SN54BCT573, SN74BCT573
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS071B – AUGUST 1990 – REVISED MARCH 2003
D ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
SN54BCT573 . . . FK PACKAGE
(TOP VIEW)
OE ¹
1D ²
2D ³
3D ⁴
4D ⁵
5D ⁶
6D ⁷
7D ⁸
8D ⁹
GND ¹⁰
20 _VCC
19 _1Q
18 _2Q
17 _3Q
16 _4Q
15 _5Q
14 _6Q
13 _7Q
12 _8Q
11 _LE
description/ordering information
3 2 1 20 19
3D ⁴
18 _2Q
4D ⁵
17 _3Q
5D ⁶
16 _4Q
6D ⁷
15 _5Q
7D ⁸
14 _6Q
9 10 11 12 13
These 8-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively
low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers.
The eight latches of the ’BCT573 devices are transparent D-type latches. While the latch-enable (LE) input is
high, the Q outputs follow the data (D) inputs. When the latch enable is taken low, the Q outputs are latched
at the logic levels that were set up at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus
lines without interface or pullup components.
To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
OE does not affect internal operations of the latches. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP – N
Tube
SN74BCT573N
SN74BCT573N
0°C to 70°C
SOIC – DW
Tube
Tape and reel
SN74BCT573DW
SN74BCT573DWR
BCT573
SOP – NS
Tape and reel SN74BCT573NSR
BCT573
CDIP – J
Tube
SNJ54BCT573J
SNJ54BCT573J
–55°C to 125°C CFP – W
Tube
SNJ54BCT573W
SNJ54BCT573W
LCCC – FK
Tube
SNJ54BCT573FK
SNJ54BCT573FK
† _{Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are}
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright  2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
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