SIRA36DP Datasheet, PDF (1/4 Pages) Vishay Siliconix – Macro Model (Sub-circuit Model)

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SPICE Device Model SiRA36DP
Vishay Siliconix
N-Channel 30 V (D-S) MOSFET
DESCRIPTION
The attached SPICE model describes the typical electrical
characteristics of the n-channel vertical DMOS. The
sub-circuit model is extracted and optimized over the -55 °C
to 125 °C temperature ranges under the pulsed 0 V to 10 V
gate drive. The saturated output impedance is best fit at the
gate bias near the threshold voltage.
A novel gate-to-drain feedback capacitance network is used
to model the gate charge characteristics while avoiding
convergence difficulties of the switched C_gd model. All
model parameter values are optimized to provide a best fit
to the measured electrical data and are not intended as an
exact physical interpretation of the device.
CHARACTERISTICS
• N-Channel Vertical DMOS
• Macro Model (Sub-circuit Model)
• Level 3 MOS
• Apply for both Linear and Switching Application
• Accurate over the -55 °C to +125 °C Temperature Range
• Model the Gate Charge
SUBCIRCUIT MODEL SCHEMATIC
D
C_GD
M2
R₁
Gy
Gx
3
DBD
G
–+
R_G
ETCV
C_GS
M1
S
Note
• This document is intended as a SPICE modeling guideline and does not constitute a commercial product datasheet. Designers should refer
to the appropriate datasheet of the same number for guaranteed specification limits.
S14-0470-Rev. A, 17-Mar-14
1
Document Number: 64322
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000