IRF720S Datasheet, PDF (1/9 Pages) Vishay Siliconix – Power MOSFET

Power MOSFET
IRF720S, SiHF720S
Vishay Siliconix
PRODUCT SUMMARY
V_DS (V)
R_DS(on) ()
Q_g (Max.) (nC)
Q_gs (nC)
Q_gd (nC)
Configuration
400
V_GS = 10 V
1.8
20
3.3
11
Single
D
D²PAK (TO-263)
G
GD
S
S
N-Channel MOSFET
ORDERING INFORMATION
Package
Lead (Pb)-free and Halogen-free
Lead (Pb)-free
Note
a. See device orientation.
D²PAK (TO-263)
SiHF720S-GE3
IRF720SPbF
SiHF720S-E3
FEATURES
• Halogen-free According to IEC 61249-2-21
Definition
• Surface Mount
• Available in Tape and Reel
• Dynamic dV/dt Rating
• Repetitive Avalanche Rated
• Fast Switching
• Ease of Paralleling
• Simple Drive Requirements
• Compliant to RoHS Directive 2002/95/EC
DESCRIPTION
Third generation Power MOSFETs from Vishay provide the
designer with the best combination of fast switching,
ruggedized device design, low on-resistance and
cost-effectiveness.
The D²PAK (TO-263) is a surface mount power package
capable of accommodating die size up to HEX-4. It provides
the highest power capability and the lowest possible
on-resistance in any existing surface mount package. The
D²PAK (TO-263) is suitable for high current applications
because of its low internal connection resistance and can
dissipate up to 2.0 W in a typical surface mount application.
D²PAK (TO-263)
SiHF720STRR-GE3^a
IRF720STRRPbF^a
SiHF720STR-E3^a
D²PAK (TO-263)
SiHF720STRL-GE3^a
-
-
ABSOLUTE MAXIMUM RATINGS (T_C = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
Drain-Source Voltage
V_DS
Gate-Source Voltage
V_GS
Continuous Drain Current
Pulsed Drain Current^a
V_GS at 10 V
T_C = 25 °C
T_C = 100 °C
I_D
I_DM
Linear Derating Factor
Linear Derating Factor (PCB Mount)^e
Single Pulse Avalanche Energy^b
E_AS
Avalanche Current^a
I_AR
Repetitive Avalanche Energy^a
E_AR
Maximum Power Dissipation
Maximum Power Dissipation (PCB Mount)^e
Peak Diode Recovery dV/dt^c
T_C = 25 °C
T_A = 25 °C
P_D
dV/dt
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)
for 10 s
T_J, T_stg
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. V_DD = 50 V, starting T_J = 25 °C, L = 30 mH, R_g = 25 , I_AS = 3.3 A (see fig. 12).
c. I_SD  3.3 A, dI/dt  65 A/μs, V_DD  V_DS, T_J  150 °C.
d. 1.6 mm from case.
e. When mounted on 1" square PCB (FR-4 or G-10 material).
LIMIT
400
± 20
3.3
2.1
13
0.40
0.025
190
3.3
5.0
50
3.1
4.0
- 55 to + 150
300^d
UNIT
V
A
W/°C
mJ
A
mJ
W
V/ns
°C
* Pb containing terminations are not RoHS compliant, exemptions may apply
Document Number: 91044
S11-1048-Rev. C, 30-May-11
www.vishay.com
1
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000