IHLP-5050CE-01_06 Datasheet, PDF (1/5 Pages) Vishay Siliconix – Low Profile, High Current Inductor

IHLP-5050CE-01
Vishay Dale
Low Profile, High Current Inductor
Manufactured under one or more of the following:
US Patents; 6,198,375/6,204,744/6,449,829/6,460,244.
Several foreign patents, and other patents pending.
STANDARD ELECTRICAL SPECIFICATIONS
Lo
INDUCTANCE
µH ± 20 % at
100 kHz, 0.25 V, 0 A
DCR mΩ DCR mΩ
TYPICAL MAX
25 °C 25 °C
HEAT RATING
CURRENT
DC AMPS³⁾
TYPICAL
SATURATION
CURRENT
DC AMPS⁴⁾
TYPICAL
0.10
0.8
0.96
43
84
0.15
1
1.2
41
75
0.22
1.1
1.3
38.5
65
0.33
1.3
1.5
36.5
62
0.47
1.6
2
32
55
0.60
1.8
2.2
29
51
0.68
2.3
2.5
28
49
0.82
2.6
3
25
44
1.0
3.3
3.5
24
40
1.5
5.1
5.5
19
35
1.8
6.5
7
16.5
30
2.2
7.2
8
16
29
3.3
11
12
12
27
4.7
14.3
15
10
24
5.6
18.3
19
9.5
19
6.8
19.8
22
9
18
8.2
24.8
28
8.5
16
10
30.4
34
7
14
NOTES:
1. All test data is referenced to 25 °C ambient
2. Operating Temperature Range - 55 °C to + 125 °C
3. DC current (A) that will cause an approximate ΔT of 40 °C
4. DC current (A) that will cause Lo to drop approximately 20 %
5. The part temperature (ambient + temp rise) should not exceed
125 °C under worst case operating conditions. Circuit design,
component placement, PWB trace size and thickness, airflow
and other cooling provisions all affect the part temperature. Part
temperature should be verified in the end application.
FEATURES
• Lowest height (3.5 mm) in this package footprint
• Shielded construction
• Frequency range up to 5.0 MHz
• Lowest DCR/µH, in this package size
RoHS
• Handles high transient current spikes without saturation ^COMPLIANT
• Ultra low buzz noise, due to composite construction
• 100 % lead (Pb)-free and RoHS compliant
APPLICATIONS
• PDA/Notebook/Desktop/Server applications
• High current POL converters
• Low profile, high current power supplies
• Battery powered devices
• DC/DC converters in distributed power systems
• DC/DC converter for Field Programmable Gate Array (FPGA)
DIMENSIONS in inches [millimeters]
0.508
[12.9]
Max.
0.138
[3.5] Max.
0.091 ± 0.01
[2.3 ± 0.3]
Typical Pad Layout
0.195
[4.95]
0.542
[13.76]
0.310
[7.87]
0.185 ± 0.01
[4.7 ± 0.3]
0.520 ± 0.015
[13.2 ± 0.38] Max.
The diagram above applies to values 0.6 µH and below.
0.508
[12.9]
Max.
0.138
[3.5] Max.
Typical Pad Layout
0.128 [3.3]
0.542
[13.8]
0.318
[8.1]
0.087 ± 0.01
[2.2 ± 0.254]
0.118 ± 0.01
[3.0 ± 0.3]
0.520 ± 0.015
[13.2 ± 0.38]
The diagram above applies to values 0.68 µH and above.
DESCRIPTION
IHLP-5050CE-01
MODEL
1.0 µH
INDUCTANCE
VALUE
GLOBAL PART NUMBER
± 20 %
INDUCTANCE
TOLERANCE
ER
PACKAGE
CODE
e3
JEDEC LEAD (Pb)-FREE
STANDARD
I
H
L
P
5
PRODUCT FAMILY
www.vishay.com
50
0
5
0
C
E
E
R
1
R
0
M
0
1
SIZE
PACKAGE
CODE
INDUCTANCE INDUCTANCE SERIES
VALUE
TOLERANCE
For technical questions, contact: [e-mail]
Document Number: 34105
Revision: 10-Aug-06