IHLP-4040DZ-11 Datasheet, PDF (1/5 Pages) Vishay Siliconix – Low Profile, High Current IHLP® Inductor

IHLP-4040DZ-11
Vishay Dale
Low Profile, High Current IHLP^® Inductor
Manufactured under one or more of the following:
US Patents; 6,198,375/6,204,744/6,449,829/6,460,244.
Several foreign patents, and other patents pending.
STANDARD ELECTRICAL SPECIFICATIONS
L_O
INDUCTANCE
µH ± 20 % AT
100 kHz,
0.25 V, 0 A
0.19
0.22
0.24
0.36
0.47
0.56
0.78
1.0
1.8
2.0
4.7
6.8
10.0
15.0
22.0
33.0
47.0
100.0
DCR
mΩ
TYP.
25 °C
0.70
0.85
0.85
1.05
1.53
1.60
1.80
2.30
4.50
5.20
12.9
17.5
27.8
40.9
60.4
87.5
132.0
249.0
DCR
mΩ
MAX.
25 °C
0.80
0.95
0.95
1.15
1.68
1.80
1.90
2.50
5.00
5.80
14.2
19.3
30.5
45.0
66.0
94.5
145.0
270.0
HEAT
RATING
CURRENT
DC AMPS³
TYP.
40
33
33
32
30
32
27
25
17
16
9.5
9.0
7.5
6.25
5.0
4.4
3.3
2.5
SATURATION
CURRENT DC
AMPS⁴ TYP.
46
44
44
30
30
22
22
20
16
14
7.6
7.5
7.1
6.0
4.5
4.0
3.0
2.25
Notes
(1) _{All test data is referenced to 25 °C ambient}
(2) _{Operating Temperature Range - 55 °C to + 125 °C}
(3) _{DC current (A) that will cause an approximate ΔT of 40 °C}
(4) _{DC current (A) that will cause Lo to drop approximately 20 %}
(5) _{The part temperature (ambient + temp rise) should not exceed}
125 °C under worst case operating conditions. Circuit design,
component placement, PWB trace size and thickness, airflow
and other cooling provisions all affect the part temperature. Part
temperature should be verified in the end application.
FEATURES
• Shielded construction
• Frequency range up to 1.0 MHz
• Lowest DCR/µH, in this package size
RoHS
• Handles high transient current spikes without ^COMPLIANT
saturation
• Ultra low buzz noise, due to composite construction
• Excellent temperature stability for inductance and saturation
• 100 % lead (Pb)-free and RoHS compliant
APPLICATIONS
• PDA/Notebook/Desktop/Server applications
• High current POL converters
• Low profile, high current power supplies
• Battery powered devices
• DC/DC converters in distributed power systems
• DC/DC converter for Field Programmable Gate Array (FPGA)
DIMENSIONS in inches [millimeters]
Typical Pad Layout
0.405
[10.3]
max
0.405
[10.3]
max
0.158
[4.0]
max
0.085 ± 0.01
[2.2 ± 0.3]
0.158
[4.0]
max
0.085 ± 0.01
[2.2 ± 0.3]
0.158
[4.0]
max
0.453 [11.5]
max
0.512
[13.0]
0.236
[6.0]
0.195
[4.95]
max
0.453 [11.5]
max
0.512
[13.0]
0.236
[6.0]
0.118 ± 0.01
[3.0 ± 0.3]
The diagram above applies to values
1.8 µH and above.
0.185 ± 0.01
[4.7 ± 0.3]
The diagram above applies to values
1.0 µH and below.
DESCRIPTION
IHLP-4040DZ-11
MODEL
2.0 µH
INDUCTANCE
VALUE
± 20 %
INDUCTANCE
TOLERANCE
ER
PACKAGE CODE
e3
JEDEC LEAD (Pb)-FREE
STANDARD
WEB CODE
sm, pi, au, cm, in,
ps, te
GLOBAL PART NUMBER
I
H
L
P
4
0
4
0
D
Z
E
R
2
R
0
M
1
1
PRODUCT FAMILY
SIZE
PACKAGE
CODE
INDUCTANCE
VALUE
TOL SERIES
Document Number: 34192
Revision: 04-Jul-08
For technical questions, contact: [e-mail]
www.vishay.com
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