AN728 Datasheet, PDF (1/10 Pages) Vishay Siliconix – Designing A Flyback Converter with Si9113 for Feeding the TE from U-Interface In ISDN

AN728
Vishay Siliconix
Designing A Flyback Converter with Si9113
for Feeding the TE from U-Interface In ISDN
Nitin Kalje and Tony Lai
INTRODUCTION
The efficiency of the converter powering the NT is extremely
important, even at power levels of a few milliwatts. To achieve
60% efficiency with an 80-mW output, the allowable power loss
in the converter is less than 54 mW. The components of these
losses include the dc and switching losses in the
semiconductors, the transformer, quiescent current overhead
in the control chip, current and voltage sense networks, power
losses from the ripple current through the input and output
capacitor ESR, resistive losses in the PCB traces, and any
external control circuit operating losses. Built on a proprietary
BiC/DMOS technology, the Si9113 integrates all the functions
necessary to minimize power consumption. Its major features
include:
D programmable start/stop
D less than 5-mA supply current in UVLO mode
D internal start-up circuit, programmable soft-start, and
power_good output.
The following sections discuss in detail design considerations
for creating an efficient 800-mW flyback converter with the
Si9113. Refer to the application circuit from Figure 6.
Start/Stop Programming
The European Telecommunication Standards Institute (ETSI)
requires the NT1 and the regenerator directed towards the line
terminal to remain at a high impedance state for as long as the
input line voltage stays below 18 V. The high impedance state
InputCurrent InputVoltage
Into +V_IN at +V_IN
A
V
1.4 m
is defined by the maximum leakage current through the
equipment and its minimum input capacitance. In this state the
leakage current must be less than 10 mA and the capacitance
more than 1 mF.
The Si9113 includes a very high input impedance-window
comparator, which can be programmed to set an accurate
undervoltage lockout (UVLO) level with adequate hysteresis.
The programmable hysteresis avoids unintentional locking of
the system during start up, especially when the system is fed
from long loops of telephone line. The comparators need a
mere 0.05-mA input bias current. Moreover, when in UVLO
mode, the Si9113 disables the internal reference generator,
soft-start, oscillator circuit, and most of the control section to
reduce the supply current below 5 mA. This keeps the total
current drawn by the converter below 10 mA and meets the
ETSI standard. See Figure 1 for the current behavior of the
Si9113 with respect to the input voltage. When the converter
is on, the V_CC is supplied by the boot-strap winding and the
internal depletion MOSFET opens.
Figure 2 shows how the hysteresis is achieved. Refer to
equations 1 and 2 to calculate the resistor values for proper
undervoltage lockout and the hysteresis.
V_START
+
R3
)
R4
R5
)
R5
8.8
(1)
V_STOP
+
R3 ) R5
R5
8.8
(2)
23.5
18.0
100 m
10 m
HiZ
Shutdown
Document Number: 71120
29-Feb-00
Operating
HiZ
Shutdown
FIGURE 1. Input Current Behaviour
Time
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