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1442 Datasheet, PDF (1/2 Pages) Vishay Siliconix – Bulk Metal Foil Technology Dual-In-Line Hermetic Resistor Networks
1442, 1445, 1446
Vishay Foil Resistors
Bulk Metal® Foil Technology
Dual-In-Line Hermetic Resistor Networks
Product may not
be to scale
Vishay Model 1442, 1445 and 1446 networks incorporate all the
performance features of Vishay Bulk Metal® Foil technology.
The 8, 14 and 16 pin side brazed DIPs are a ceramic package.
Ceramic has the advantage of electrical isolation on the underside,
and, in DIP form, a favorable pin arrangement when two networks
are to be placed side by side and connected together.
Review data sheet “7 Technical Reasons to Specify Bulk
Metal® Foil Resistor Networks.”
Networks are built to your requirements. Send your schematic
and electrical requirements to the Applications Engineering
Department. (See data sheet “Network Worksheet.”) A unique
part number will be assigned which defines all aspects of your
network.
FIGURE 1 - PACKAGE SIZES AND CHARACTERISTICS
L
B
0.008 to 0.016
(0.20 to 0.41)
W
0.200 MAXIMUM
(5.08)
0.300 ±0.010
(7.62 ±0.25)
LL
NOTE:
NO. 1 LEAD
0.015 to 0.022
0.100
(2.54)
TYPICAL
(0.38
to
0.56)
1. These networks utilize Vishay Bulk Metal® Foil resistor chips V5X5 and V15X5 or VTF15X5 Thin Film chips.
2. The V5X5 and V15X5 chips have maximum resistance values of 10K and 33K respectively in Bulk Metal® Foil and 500K in
VTF15X5 Thin Film chips.
3. The V5X5 and V15X5 chip(s) can be intermixed in a package.
VISHAY
MODEL
NO. OF
PINS
MAXIMUM DIMENSIONS in Inches (mm)
L
W
B
LL
CHIP CAPACITY MAXIMUM POWER RATING
V5X5 V15X5 (WATTS) @ +70°C
1442
8
0.520 ±0.020 0.295 ±0.010
0.054
0.125 minimum
12
4
0.4
(13.21 ±0.51) (7.49 ±0.025)
(1.37)
(3.18)
1445
14
0.740 ±0.045 0.270 +0.035/–0.030 0.046
0.135 +0.015/–0.010 30
10
1.2
(18.80 ±1.14) (6.86 +0.89/–0.76)
(1.17)
(3.43 +0.38/–0.25)
1446
16
0.780 ±0.030 0.290 ±0.008 0.040 to 0.070 0.135 +0.015/–0.010 36
12
1.4
(19.81 ±0.76)
(7.37 ±0.20)
(1.01 to 1.78) (3.43 +0.38/–0.25)
FIGURE 2 - SAMPLE CIRCUIT DESIGN AND CHIP LAYOUT
7
6
NOTE:
Usable area is represented by
the dotted lines— a rectangle
8
5
0.150 Inches x 0.200 Inches.
Illustrations not to scale. Chips
shown undersize for clarity.
Drawing view is from the top
looking down into the package.
1
4
2
3
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126
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7
6
5
1
2
3
4
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Document Number: 63032
Revision 31-Jul-02