PRM48JH480X250A00 Datasheet, PDF (36/44 Pages) Vicor Corporation – Pin selectable operating mode

PRM48JH480x250A00
Control Loop Compensation Requirements
(Remote Sense Operation)
In order to properly compensate the control loop, all components
which contribute to the closed loop frequency response should be
identified and understood. Figure 24 shows the AC small signal
model for the module. Modulator DC gain G_CN and powertrain
equivalent resistance r_{EQ_OUT} are shown. These modeling parameters
will support a design cut-off frequency up to 50kHz.
Standard Bode analysis should be used for calculating the error
amplifier compensation and analyzing the closed loop stability. The
recommended stability criteria are as follows:
1) Phase Margin > 45º: for the closed loop response, the phase
should be greater than 45º where the gain crosses 0 dB.
2) Gain Margin > 10dB : The closed loop gain should be lower than -
10dB where the phase crosses 0º.
3) Gain Slope = -20dB/decade : The closed loop gain should have a
slope of -20dB/decade at the crossover frequency.
The compensation characteristics must be selected to meet these
stability criteria. Refer to Figure 37 for a local sense, voltage-mode
control example based on the configuration in Figure 36. In this
example, it is assumed that the maximum crossover frequency
(F_CMAX) has been selected to occur between B and C. Type-2
compensation (Curve IJKL) is sufficient in this case.
The following data must be gathered in order to proceed:
n Modulator Gain G_CN: See Figures 18, 19, 20
n Powertrain equivalent resistance r_EQ: See Figures 18, 19, 20
n Internal output capacitance: see Figure 13
n External output capacitance value
In the case of ceramic capacitors, the ESR can be considered low
enough to push the associated zero well above the frequency of
interest. Applications with high ESR capacitor may require a
different type of compensation, or cascade control.
The system poles and zeros of the closed loop can then be defined as
follows:
n Powertrain pole, assuming the external capacitor ESR can be
neglected:
R  _{rr u} ^RR _{COUT _ EXT}
EQ _ OUT
EQ _ OUT
LOAD
LOAD
n Main pole frequency:
 ^FP
5
2 ʌu
r_{EQ _ OUT} u R_LOAD
r_{EQ _ OUT} R_LOAD
1
u
C C _{OUT _ INT}
OUT _ EXT
n Compensation Mid-Band Gain:
G _MB

20 log
R₃
R₁
(8)
n Compensation Zero:
F_Z1

1
2 ʌu R₃u C₁
(9)
n Compensation Pole:
F_{P 2}

2 ʌu
1
R₃ u C₁ u C₂
C₁ C₂
and for F_P2>>F_Z1 (C₁ + C₂ ≈ C₁):
F_{P 2}
5
2/
u
1
R₃
u C₂
(10)
80
60 ^I Compensation Gain
40 _E
F
PRM Open Loop Min Load
A
20 _{PRM Open Loop Max Load}
0
-20
-40
Open Loop Gain vs. Frequency
Application’s op-amp GBW
B
J
FCMIN F_CMAX
Frequency, Log scale
(y-intercept is application specific)
K
L
C
G
Figure 38 — Reference asymptotic Bode plot for the considered system
PRM^TM Regulator
Page 36 of 44
Rev 1.2
11/2015
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