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PI3303-00-LGIZ Datasheet, PDF (34/42 Pages) Vicor Corporation – 8 V to 36 Vin Cool-Power ZVS Buck Regulator Family
The PI33xx-x0 default for SYNCI is to sync with respect to the
falling edge of the applied clock providing 180° phase shift from
SYNCO. This allows for the paralleling of two PI33xx-x0 devices
without the need for further user programming or external sync
clock circuitry. The user can change the SYNCI polarity to sync
with the external clock rising edge via the I2C data bus (PI33xx-20
device versions only).
By connecting the EAO pins and SGND pins of each module
together the units will share the current equally. When the TRK
pins of each unit are connected together, the units will track each
other during soft-start and all unit EN pins have to be released
to allow the units to start (See Figure 59). Also, any fault event in
any regulator will disable the other regulators. The two regulators
will be out of phase with each other reducing output ripple (refer
to Switching Frequency Synchronization).
To provide synchronization between regulators over the entire
operational frequency range, the Parallel Good (PGD) pin must
be connected to the lead regulator’s (#1) SYNCI pin and a 2.5
kΩ Resistor, R1, must be placed between SYNCO (#2) return and
the lead regulator’s SYNCI (#1) pin, as shown in Figure 59. In
this configuration, at system soft-start, the PGD pin pulls SYNCI
low forcing the lead regulator to initialize the open-loop startup
synchronization. Once the regulators reach regulation, SYNCI is
released and the system is now synchronized in a closed-loop
configuration which allows the system to adjust, on the fly, when
any of the individual regulators begin to enter variable frequency
mode in the loop.
Multi-phasing three regulators is possible (PI33xx-20 only) with
no change to the basic single-phase design. For more information
about how to program phase delays within the regulator, please
refer to Picor application note PI33xx-2x Multi-Phase Design
Guide.
I2C Interface Operation
PI33xx-20 devices provide an I2C digital interface that enables the
user to program the EN pin polarity (from high to low assertion)
and switching frequency synchronization phase/delay. These are
one time programmable options to the device.
Also, the PI33xx-20 devices allow for dynamic VOUT margining via
I2C that is useful during development (settings stored in volatile
memory only and not retained by the device). The PI33xx-20 also
have the option for fault telemetry including:
nnFast/Slow current limit
nnOutput voltage high
nnInput overvoltage
nnInput undervoltage
nnOver temperature protection
For more information about how to utilize the I2C interface please
refer to Picor application note PI33xx-2x I2C Digital
Interface Guide.
PI33xx-x0
Application Description
Output Voltage Trim
The PI33xx-x0 family of Buck Regulators provides seven common
output voltages: 1.0 V, 1.8 V, 2.5 V, 3.3 V, 5.0 V, 12 V and 15 V.
A post-package trim step is implemented to offset any resistor
divider network errors ensuring maximum output accuracy. With
a single resistor connected from the ADJ pin to SGND or REM,
each device’s output can be varied above or below the nominal
set voltage (with the exception of the PI3311-X0 which can only
be above the set voltage of 1 V).
Device
Output Voltage
Set
Range
PI3311-x0
1.0 V
1.0 to 1.4 V
PI3318-x0
1.8 V
1.4 to 2.0 V
PI3312-x0
2.5 V
2.0 to 3.1 V
PI3301-x0
3.3 V
2.3 to 4.1 V
PI3302-x0
5.0 V
3.3 to 6.5 V
PI3303-x0
12 V
6.5 to 13.0 V
PI3305-x0
15 V
10.0 to 16.0 V
Table 2 — PI33xx-x0 family output voltage range
The remote pin (REM) should always be connected to the VOUT
pin, if not used, to prevent an output voltage offset. Figure 60
shows the internal feedback voltage divider network.
R4
R1
-
+
R2
1.0 Vdc
VOUT
REM
Rlow
ADJ
SGND
Rhigh
Figure 60 — Internal resistor divider network
R1, R2, and R4 are all internal 1.0 % resistors and Rlow and Rhigh
are external resistors for which the designer can add to modify
VOUT to a desired output. The internal resistor value for each
regulator is listed below in Table 3.
Cool-Power®
Page 34 of 42
Rev 2.0
02/2016
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