PI3312-00-LGIZ Datasheet, PDF (33/42 Pages) Vicor Corporation – 8 V to 36 Vin Cool-Power ZVS Buck Regulator Family

Output Current Limit Protection
PI33xx-x0 has two methods implemented to protect from output
short or over current condition.
Slow Current Limit protection: prevents the output load from
sourcing current higher than the regulator’s maximum rated
current. If the output current exceeds the Current Limit (I_{OUT_CL})
for 1024 us, a slow current limit fault is initiated and the regulator
is shutdown which eliminates output current flow. After Fault
Restart Delay (t_{FR_DLY}), a soft-start cycle is initiated. This restart
cycle will be repeated indefinitely until the excessive load
is removed.
Fast Current Limit protection: PI33xx-x0 monitors the regulator
inductor current pulse-by-pulse to prevent the output from
supplying very high current due to sudden low impedance short
(50 A Typical). If the regulator senses a high inductor current
pulse, it will initiate a fault and stop switching until Fault Restart
Delay ends and then initiate a soft-start cycle.
Both the Fast and Slow current limit faults are stored in a Fault
Register and can be read and cleared (PI33xx-20 device versions
only) via I²C data bus.
Input Undervoltage Lockout
If V_IN falls below the input Undervoltage Lockout (UVLO)
threshold, but remains high enough to power the internal
bias supply, the PI33xx-x0 will complete the current cycle and
stop switching. If V_IN recovers within 128 switching cycles,
the PI33xx-x0 will resume normal operation. If this time limit
is exceeded, the system will enter a low power state and
initiate a fault.The system will restart once the input voltage is
reestablished and after the Fault Restart Delay. A UVLO fault is
stored in a Fault Register and can be read and cleared (PI33xx-20
device versions only) via I²C data bus.
Input Overvoltage Lockout
If V_IN exceeds the input Overvoltage Lockout (OVLO) threshold
(VOVLO), while the controller is running, the PI33xx-x0 will
complete the current cycle and stop switching. If V_IN recovers
within 128 switching cycles, the PI33xx-x0 will resume normal
operation. Otherwise, the system will enter a low power state
and sets an OVLO fault. The system will resume operation when
the input voltage falls below 98% of the OVLO threshold and
after the Fault Restart Delay. The OVLO fault is stored in a Fault
Register and can be read and cleared (PI33xx-20 device versions
only) via I²C data bus.
Output Overvoltage Protection
The PI33xx-x0 family is equipped with output Overvoltage
Protection (OVP) to prevent damage to input voltage sensitive
devices. If the output voltage exceeds 20% of its set regulated
value, the regulator will complete the current cycle, stop
switching and issue an OVP fault. The system will resume
operation once the output voltage falls below the OVP threshold
and after Fault Restart Delay. The OVP fault is stored in a Fault
Register and can be read and cleared (PI33xx-20 device versions
only) via I²C data bus.
PI33xx-x0
Overtemperature Protection
The internal package temperature is monitored to prevent internal
components from reaching their thermal maximum. If the Over
Temperature Protection Threshold (OTP) is exceeded (T_OTP), the
regulator will complete the current switching cycle, enter a low
power mode, set a fault flag, and will soft-start when the internal
temperature falls below Overtemperature Restart Hysteresis
(T_{OTP_HYS}). The OTP fault is stored in a Fault Register and can be
read and cleared (PI33xx-20 device versions only) via I²C data bus.
Pulse Skip Mode (PSM)
PI33xx-x0 features a PSM to achieve high efficiency at light loads.
The regulators are setup to skip pulses if EAO falls below a PSM
threshold. Depending on conditions and component values, this
may result in single pulses or several consecutive pulses followed
by skipped pulses. Skipping cycles significantly reduces gate drive
power and improves light load efficiency. The regulator will leave
PSM once the EAO rises above the Skip Mode threshold.
Variable Frequency Operation
Each PI33xx-x0 is preprogrammed to a base operating frequency,
with respect to the power stage inductor (see Table 4), to operate
at peak efficiency across line and load variations. At low line
and high load applications, the base frequency will decrease to
accommodate these extreme operating ranges. By stretching the
frequency, the ZVS operation is preserved throughout the total in-
put line voltage range therefore maintaining optimum efficiency.
Parallel Operation
Paralleling modules can be used to increase the output current
capability of a single power rail and reduce output voltage ripple.
V_IN
C_IN
R1
SYNCO(#2)
SYNCI(#2)
EN(#2)
EAO(#2)
TRK(#2)
V_IN
PGND
L1
VS1
V_OUT
PI33xx
PGD _(#1) REM
SYNCI
SYNCO
EN
EAO
TRK
SGND
C_OUT
V_IN
C_IN
SYNCO(#1)
SYNCI(#1)
EN(#1)
EAO(#1)
TRK(#1)
L1
V_IN
PGND
VS1
V_OUT
PI33xx
PGD _(#2) REM
SYNCI
SYNCO
EN
EAO
TRK
SGND
C_OUT
Figure 59 — PI33xx-x0 parallel operation
V_OUT
Cool-Power®
Page 33 of 42
Rev 2.0
02/2016
vicorpower.com
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