PI2007 Datasheet, PDF (2/19 Pages) Vicor Corporation – Universal High Side Active ORing Controller IC

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Pin Description
Pin Name Pin
Number
Description
PGND
1
Gate Turn Off Switch Return: This pin is the high current return path for the gate driver
during turn off. Connect this pin to the low side of the VC coupling capacitor and SGND.
Gate Drive Output: This pin drives the gate of the external N-channel MOSFET. Under
normal operating conditions and when V_SP-SN > 6mV, the GATE pin pulls high to
GATE
2
approximately 2*VC with respect to the SGND pin. The controller turns the gate off
during a reverse current fault that is below the reverse voltage threshold (-6mV) and
when VC is in Under Voltage (7.15V).
Controller Input Supply: This pin is the supply pin for the control circuitry and gate
driver. Connect a 1μF capacitor between the VC pin and the SGND pin. Voltage on this
VC
3
pin is regulated to 11.7V with respect to SGND by an internal shunt regulator. For high
voltage supply applications connect a shunt resistor between the SGND and PGND pins
and the supply return, as shown in Figure 2.
SGND
4
VC Return: This pin is the return (ground) for the control circuitry. Connect this pin to
the low side of VC decoupling capacitor.
Controller Input Supply With Limiting Resistor: This pin is connected internally to VC
VR
5
through a 420Ω resistor needed for Bus voltages greater than 10V and less than 14V.
Leave this pin open if unused.
Positive Sense Input: Connect SP pin to the Source pin of the external N-channel
SP
6
MOSFETs. The polarity of the voltage difference between SP and SN provides an
indication of current flow direction through the MOSFET.
NC
7, 10
Not Connected: Leave pins floating.
Negative Sense Input: Connect SN to the Drain pin of the external N-channel MOSFET.
SN
8
The polarity of the voltage difference between SP and SN provides an indication of
current flow direction through the MOSFET.
Fault Status Output: This open collector pin pulls low to indicate one of the several
potential fault conditions may exist. The FT pin will pull low after a reverse or forward
fault has been detected with a defined delay time (8μs). In addition, the FT pin will pull
FT
9
low when the controller input voltage is below the VC under-voltage threshold V_VC-SGND <
7V. When V_VC-SGND > 7.15V and 6mV < V_SP-SN < 275mV this pin clears (High). In high
voltage applications this output must be translated with reference to the system return
with external circuitry, see Figure 19. Leave this pin open if unused.
Package Pin-Outs
10 Lead DFN (3mm x 3mm)
Top view
Picor Corporation • picorpower.com
PI2007
Rev 1.3
Page 2 of 19