VIV0104THJ Datasheet, PDF (13/16 Pages) Vicor Corporation – DC to DC Voltage Transformation

VIV0104THJ
6.0 FUSE SELECTION
V•I Chips are not internally fused in order to provide flexibility
in configuring power systems. Input line fusing of V•I Chips is
recommended at system level, to provide thermal protection in
case of catastrophic failure.
The fuse shall be selected by closely matching system
requirements with the following characteristics:
• Current rating (usually greater than maximum VTM current)
• Maximum voltage rating (usually greater than the maximum
possible input voltage)
• Ambient temperature
• Nominal melting I²t
7.0 CURRENT SHARING
The SAC topology bases its performance on efficient transfer
of energy through a transformer, without the need of closed
loop control. For this reason, the transfer characteristic can be
approximated by an ideal transformer with some resistive drop
and positive temperature coefficient.
This type of characteristic is close to the impedance
characteristic of a DC power distribution system, both in
behavior (AC dynamic) and absolute value (DC dynamic).
When connected in an array (with same K factor), the VTM
module will inherently share the load current with parallel
units, according to the equivalent impedance divider that the
system implements from the power source to the point of load.
It is important to notice that, when successfully started, VTMs
are capable of bi-directional operations (reverse power transfer
is enabled if the VTM input falls within its operating range and
the VTM is otherwise enabled). In parallel arrays, because of
the resistive behavior, circulating currents are never
experienced, because of energy conservation law.
General recommendations to achieve matched array
impedances are (see also AN016 for further details):
• to dedicate common copper planes within the PCB to
deliver and return the current to the modules
• to provide the PCB layout as symmetric as possible
• to apply same input/output filters (if present) to each unit
VIN
+
–
DC
ZIN_EQ1
ZIN_EQ2
VTM1
RO_1
ZOUT_EQ1
VOUT
VTM2
RO_2
Z_{OUT_EQ2}
Load
Figure 17 – VTM Array
ZIN_EQn
VTMn
R_{O_n}
ZOUT_EQn
v i c o r p o w e r. c o m
V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 1.3
9/2009
Page 13 of 16