FX-702_10 Datasheet, PDF (5/8 Pages) Vectron International, Inc – Low Jitter VCSO Frequency Translator

FX702 YWW
CCC-CCC
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Figure 5. Outline Diagram
Table 7. Pin Functions
Pad #
Symbol
1
BRCLK
2
LD¹
3
GND
4
MODE²
5
GND
I/O
Level
Function
I
NC or LVPE- NC or
CL, LVDS For External divider application = PD Feedback Frequency
O
CMOS Lock Detect
Logic 0 = FX Locked
Logic 1 - No Input
Output transitioning = Out of Lock
GND
Supply Case and electrical ground
I
CMOS FX Operating Mode
Logic 0 = Standard PLL (Normal Setting)
Logic 1 = FIN coupled to FOUT
GND
Supply Case and electrical ground
6
LFN
Analog Loop Filter Node
7
CLFN
Analog Complementary Loop Filter Node
8
FOUT
9
CFOUT
10
VCC
11
CFIN^4,5
12
FIN^4,5
O
LVPECL or Frequency Output
LVDS
O
LVPECL or Complementary Frequency Output
LVDS
I
Supply Power Supply Voltage (+3.3V ±5%)
I
LVPECL Complemetary Input Frequency
For CMOS inouts, AC-couple unused inputto ground or negative supply
I
CMOS or Input Frequency
LVPECL
13
GND
GND
Supply Case and electrical ground
14
CBRCLK^3,4
I
NC or LVPE- NC or
CL, LVDS For External divider applications = Comp. PD Feedback Frequency
1.
It is recommended that a buffer driver is used for best noise isolation.
2.
Do not leave the MODE pin floating, it should be set to logic 0 or ground for normal operation.
3.
BRCLK and CBRCLK should be left floating if not used.
4.
FIN, CFIN, BRCLK, and CBRCLK have internal pull-up/pull-down resistors and it is recommended to AC couple these inputs.
5.
Best jitter is realized with a differential input.
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Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
5
Rev: 06Oct2010