FX-700 Datasheet, PDF (3/8 Pages) Vectron International, Inc – Low Jitter Frequency Translator

FX-700 Low Jitter Frequency Translator
Outline Diagram
13 12 11 10 9
14 ^FLACGNK 8
15
A3/K2
7
16
VI YWW
6
1 2345
Pin Out
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Symbol
VDD
VDA
VCOUT
Tri-state¹
C1
FIN
GND
LD²
GNDB
FOUT
VDB
VCXOIN
VCXOOUT
VDO
N.C.
VCIN
Function
Digital PLL Supply (3.3 V +/- 10% or 5.0 V +/- 10%)
Analog PLL Supply (3.3 V +/- 10% or 5.0 V +/- 10%)
Control Voltage
Logic Low = Output Disable / Logic High = Output Enabled
Passive Loop Filter Node
Input Frequency
Cover and Electrical Ground
Lock Detect
Output Buffer Ground
Output Frequency
Output Buffer Supply (3.3V +/-10% or 5.0V +/-10%)
VCXO Input
VCXO Output
VCXO Supply (3.3 V +/- 10% or 5.0 V +/- 10%)
No Internal Connection Made
VCXO Control Voltage Input
1 Tri-state must be driven to a logic high or a logic low, there is no internal pull up or pull down resistor (tie pin to VDD for
PLL operation).
2 LD is an open collector output requiring a 30k ohm minimum pull-up resistor to VDD. LD output is logic high under
locked condition, logic low for no input at FIN, and for "out-of-lock" condition LD transitions between logic low and high
at the phase detector frequency.
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • Web: www.vectron.com
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