FX-702-SYNCE-156M250000 Datasheet, PDF (2/7 Pages) Vectron International, Inc – Complete VCSO Based Phase Lock Loop

Performance Specifications
Table 1. Electrical Performance
Parameter
Symbol
Min
Typical Maximum
Frequency ^{1, 2, 3}
Input Frequency
Output Frequency
Capture Range^{1, 2, 3}
F
156.25
IN
F
156.25
OUT
APR
±100
Supply
Voltage ^{2, 3}
Current (No Load) ³
LVCMOS Input ^{2, 3}
Input High Voltage
Input Low Voltage
LVPECL Input
Peal-Peak Amplitude Swing ^{6, 7}
V
2.97
3.3
3.63
CC
I
100
CC
V
2.0
V
IH
CC
V
0
0.8
IL
0.20
3.00
Lock Detect Output
Output High Voltage
Logic Low Voltage
V
0.9*V
OH
CC
V
OL
0.1*V
CC
Outputs
Mid Level - LVPECL ^{2, 3}
Swing - LVPECL ^{2, 3}
V -1.4
CC
450
V -1.25
CC
600
V -1.0
CC
950
Current ⁵
Rise Time ^{4, 5}
Fall Time ^{4, 5}
Symmetry ^{2, 3}
I
20
OUT
t
400
R
t_F
400
SYM
45
50
55
Jitter Generation - 156.25 MHz output
(12kHz-20MHz BW) ⁵
Φ
J
150
200
Operating Temp
T
OP
1. See Standard Frequencies and Ordering Information.
-40/85
2. Parameters are tested with production test circuit below (Fig 1).
3. Parameters are tested at ambient temperature with test limits guard banded for specified operating temperature.
4. Measured from 20% to 80% of a full output swing (Fig 2).
5. Not tested in production, guaranteed by design, verified at qualification.
6. Minimum Input Low Voltage not to exceed 2.125 V. Minimum Input High Voltage not to go below 1.49 V.
7. AC coupling is recommended. There is an internal pull-up and pull-down resistor on all clock inputs (Fin, BRCLK).
Units
MHz
MHz
V
mA
V
V
V
V
V
V
mV-pp
mA
ps
ps
%
fs-rms
0C
Figure 1. LVPECL Test Circuit
Figure 2. 10K LVPECL Waveform
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Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com
Rev: 22Sep2009