COG-VL248160-02 Datasheet, PDF (11/12 Pages) Varitronix international limited – 248x160 dots, FSTN, black & white, positive, transflective, LCD graphic module.

VL-PS-COG-VL248160-02 REV.A
(COG-VL248160)
NOV/2008
PAGE 11 OF 12
5.3 Power-Up Sequence
UC1698u power-up sequence is simplified by builtin “Power Ready” flags and the automatic
invocation of System-Reset command after Power-ON-Reset.
System programmers are only required to wait 150 ms before the CPU starting to issue commands to
UC1698u. No additional time sequences are required between enabling the charge pump, turning on
the display drivers, writing to RAM or any other commands. However, while turning on VDD,
VDD2/3 should be started not later than VDD.
Delay allowance between VDD and VDD2/3 is illustrated as Figure 7.
Figure 5: Reference Power-Up Sequence
5.4 Power-Down Sequence
To prevent the charge stored in capacitors CBX+, CBX–, and CL from damaging the LCD, when
VDD is switched off, use Reset mode to enable the built-in draining circuit and discharge these
capacitors.
The draining resistor is 10KΩ for both VLCD and VB+. It is recommended to wait 3 x RC for
VLCD and 1.5 x RC for VB+. For example, if CL is 0.1uF, then the draining time required for
VLCD is ~3mS.
When internal VLCD is not used, UC1698u will NOT drain VLCD during RESET. System designers
need to make sure external VLCD source is properly drained off before turning off VDD.
Figure 6:Reference Power-Down Sequence
Figure 7: Delay allowance between VDD and VDD2/3