SI4567DY Datasheet, PDF (2/4 Pages) Vaishali Semiconductor – Dual N- and P-Channel 40-V (D-S) MOSFET

SPICE Device Model Si4567DY
Vishay Siliconix
SPECIFICATIONS (T_J = 25°C UNLESS OTHERWISE NOTED)
Parameter
Symbol
Test Condition
Static
Gate Threshold Voltage
On-State Drain Current^a
V_GS(th)
I_D(on)
Drain-Source On-State Resistance^a
r_DS(on)
Forward Transconductance^a
g_fs
Diode Forward Voltage^a
V_SD
Dynamic^b
V_DS = V_GS, I_D = 250 µA
V_DS = V_GS, I_D = −250 µA
V_DS = 5 V, V_GS = 10 V
V_DS = −5 V, V_GS = −10 V
V_GS = 10 V, I_D = 4.1 A
V_GS = −10 V, I_D = −3.6 A
V_GS = 4.5 V, I_D = 3.8 A
V_GS = −4.5 V, I_D = −2.9 A
V_DS = 15 V, I_D = 4.1 A
V_DS = −15 V, I_D = −3.6 A
I_S = 1.5 A, V_GS = 0 V
I_S = −1.6 A, V_GS = 0 V
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
C_ISS
C_OSS
C_RSS
N-Channel
V_DS = 20 V, V_GS = 0 V, f = 1 MHz
P-Channel
V_DS = − 20 V, V_GS = 0 V, f = 1 MHz
Total Gate Charge
V_DS = 20 V, V_GS = 10 V, I_D = 5 A
V_DS = − 20 V, V_GS = −10 V, I_D = − 5 A
Q_g
Gate-Source Charge
Gate-Source Charge
N-Channel
V_DS = 20 V, V_GS = 4.5 V, I_D = 5 A
Q_gs
P-Channel
V_DS = − 20 V, V_GS = −4.5 V, I_D = − 5 A
Q_gs
Notes
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%.
b. Guaranteed by design, not subject to production testing.
Simulated Measured
Data
Data
Unit
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
1.4
1.9
97
67
0.049
0.056
0.056
0.097
9
6.3
0.72
0.80
V
A
0.048
0.058
Ω
0.056
0.097
15
S
7
0.80
V
−0.80
N-Ch
471
P-Ch
567
N-Ch
53
P-Ch
76
N-Ch
25
P-CH
57
N-Ch
6.5
P-Ch
10.5
N-Ch
3.3
P-Ch
5.7
N-Ch
1.1
P-Ch
1.5
N-Ch
1.4
P-Ch
2.7
355
480
50
pF
80
29
56
8
12
3.7
6
nC
1.1
1.5
1.4
2.7
www.vishay.com
2
Document Number: 74147
S-60243Rev. A, 20-Feb-06