VT73LVP10 Datasheet, PDF (1/3 Pages) Vaishali Semiconductor – TTL to Differential LVPECL Translator

Preliminary
VT73LVP10
TTL to Differential LVPECL Translator
with Enable
Applications
•= PECL clock source
General Description
The Vaishali VT73LVP10 is a general purpose TTL (CMOS) to differential LVPECL translator, with active-LOW
enable. The device operates from a single 3.3V supply. When /EN is LOW or open circuit, the device accepts
an LVTTL or LVCMOS input and provides differential LVPECL outputs referenced to the positive supply rail.
When /EN is HIGH, the Q output is set to the LOW state and QN output is set to the HIGH state.
Features
•= 700ps typical propagation delay
•= Differential LVPECL outputs
•= Flow-through pinout
•= -40^o C to +85^o C operating temperature range
•= 5V - tolerant inputs
•= ESD rating >2000V (Human Body
Model) or >200V (Machine Model)
•= Available as die, 8-pin SOIC or 8 pin
MSOP package
Figure 1. Functional Block Diagram & Pin Assignment
8 pin SOIC/ MSOP
NC ₁
Q2
LVPECL
QN ₃
/EN 4
100kΩ
8 V_DD
TTL/ _{7 D}
CMOS
6 NC
5 GND
2002-01-15
Vaishali Semiconductor
Page 1
www.vaishali.com
747 Camden Avenue, Suite C Campbell CA 95008
Ph. 408.377.6060
MDST-0014-07
Fax [phone]