M1725_15 Datasheet, PDF (9/10 Pages) Unisonic Technologies – 16-BIT,96KHZ STEREO AUDIO D/A CONVERTER

M1725
CMOS IC
„ FUNCTIONAL DESCRIPTION
SYSTEM CLOCK
The system clock (SCKI) must be either 256 f_S or 384 f_S, where f_S is the audio sampling frequency (LRCIN),typically
32kHz, 44.1kHz or 48kHz. The system clock is used to operate the digital filter and the noise shaper. Timing
conditions for SCKI are shown in Figure4.
M1725 includes a system clock detection circuit which auto-matically detects the frequency, either 256 f_S or 384 f_S.
The system clock should be synchronized with LRCIN,but M1725 can compensate for phase differences. If the
phase difference between LRCIN and system clock is greater than ±6 bit clocks (BCKIN), the synchronization is
performed automatically. The analog outputs are forced to a bipolar zero state (VCC/2) during the synchronization
function. The typical system clock frequency inputs vs sampling rate for the M1725 is shown below.
SAMPLING RATE(LRCIN)(kHz)
32
44.1
48
SYSTEM CLOCK FREQUENCY(MHz)
256 f_S
384 f_S
8.192
12.288
11.2896
16.934
12.288
18.432
INPUT DATA FORMAT
M1725 can accept input data in either normal (MSB-first, right-justified) or I²S format by applying LOW or HIGH
voltage level on FORMAT-pin.
FORMAT
Low
High
INPUT DATA FORMAT SELECTED
Normal Format (MSB-first, right-justified)
I2S Format (Philips serial data protocol)
DE-EMPHASIS CONTROL
DM-pin enables M1725’s de-emphasis function. De-emphasis operates only at 44.1kHz.
DM
DE-EMPHASIS FUNCTION SELECTED
Low
De-emphasis ON (44.1kHz)
High
De-emphasis OFF
RESET
M1725 includes an internal power-on reset circuit. The power-on reset initializes and has an initialization period
equal to 1024 system clock periods after VCC>2.2V. During the initialization period, the DAC outputs are invalid, and
the analog outputs are forced to VCC/2.
UNISONIC TECHNOLOGIES CO., LTD
www.unisonic.com.tw
9 of 10
QW-R502-427.A