M1008 Datasheet, PDF (5/11 Pages) Unisonic Technologies – 16-BIT CCD/CIS ANALOG SIGNAL PROCESSOR

M1008
„ TIMING SPECIFICATION
PARAMETER
3-Channel Pixel Rate
2-Channel Pixel Rate
1-Channel Pixel Rate
ADCCLK Pulse Width
CDSCLK1 Pulse Width
CDSCLK2 Pulse Width
CDSCLK1 Falling to CDSCLK2 Rising
ADCCLK Rising to CDSCLK1 Falling
ADCCLK Rising to CDSCLK2 Falling
Analog Sampling Delay
3-CHANNEL Mode Only
CDSCLK2 Falling to CDSCLK1 Rising
CDSCLK2 Falling to ADCCLK Rising
2-CHANNEL Mode Only
CDSCLK2 Falling to ADCCLK Rising
CDSCLK1 Rising to ADCCLK Rising
CDSCLK2 Falling to CDSCLK1 Rising
1-CHANNEL Mode Only
CDSCLK2 Falling to ADCCLK Rising
CDSCLK1 Rising to ADCCLK Falling
CDSCLK2 Falling to CDSCLK1 Rising
SERIAL INTERFACE
Maximum SCLK Frequency
SLOAD to SCLK Setup Time
SCLK to SLOAD Hold Time
SDATA to SCLK Rising Setup Time
SCLK Rising to SDARA Hold Time
Falling to SDATA Valid
DATA OUTPUT
Output Delay
Latency(Pipeline Delay)
Preliminary
SYMBOL
t_PRA
t_PRB
t_PRC
t_ADCLK
t_C1
t_C2
t_C1C2
t_ADC1
t_ADC2
t_AD
ta_C2C1
ta_C2ADR
tb_C2ADR
tb_C1ADR
tb_C2C1
tc_C2ADR
tc_C1ADF
tc_C2C1
f_SCLK
t_LS
t_LH
t_DS
t_DH
t_RDV
t_OD
TEST CONDITION
CMOS IC
MIN TYP MAX UNIT
100
ns
66
ns
40
ns
16
ns
12
ns
12
ns
0
ns
0
ns
0
ns
5
ns
30
30
30
15
15
20
0
15
10
10
10
10
10
10
8
9
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
Cycles
UNISONIC TECHNOLOGIES CO., LTD
www.unisonic.com.tw
5 of 11
QW-R502-434.a