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CD4541_15 Datasheet, PDF (5/7 Pages) Unisonic Technologies – PROGRAMMABLE TIMER | |||
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CD4541
CMOS IC
ï® OPERATING CHARACTERISTICS
With Auto Reset pin set to a â0â the counter circuit is initialized by turning on power. Or with power already on, the
counter circuit is reset when the Master Reset pin is set to a â1â. Both types of reset will result in synchronously
resetting all counter stages independent of counter state.
The RC oscillator frequency is determined by the external RC network, i.e.:
and RS ~ 2 RTC where RSâ§10 kâ¦
The time select inputs (A and B) provide a two-bit address to output any one of four counter stages (28, 210, 213,
and 216). The 2n counts as shown in the Division Ratio Table represent the Q output of the Nth stage of the counter.
When A is â1â, 216 is selected for both states of B.
However, when B is â0â, normal counting is interrupted and the 9th counter stage receives its clock directly from
the oscillator (i.e., effectively outputting 28).
The Q/Q select output control pin provides for a choice of output level. When the counter is in a reset condition
and Q/Q select pin is set to a â0â the Q output is a â0â. Correspondingly, when Q/Q select pin is set to a â1â the Q
output is a â1â.
When the mode control pin is set to a â1â, the selected count is continually transmitted to the output. But, with
mode pin â0â and after a reset condition the RS flip-flop resets (see Logic Diagram), counting commences and after
2n-1 counts the RS flip-flop sets which causes the output to change state. Hence, after another 2n-1 counts the output
will not change. Thus, a Master Reset pulse must be applied or a change in the mode pin level is required to reset
the single cycle operation.
Oscillator Circuit Using RC Configuration
3
INTERNAL
RESET
2
1
RS
CTC
RTC
TO CLOCK
CIRCUIT
UNISONIC TECHNOLOGIES CO., LTD
www.unisonic.com.tw
5 of 7
QW-R502-037.D
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