UM3502QA Datasheet, PDF (9/13 Pages) Union Semiconductor, Inc. – Low-Profile, 600mA, Synchronous Step-Down Converter with Integrated Inductor

UM3502QA
Applications Information
Output Voltage Setting
The output voltage is set by a resistive divider according to the following formula:
𝑅2
𝑉_{𝑂𝑈𝑇} =0.6V 1 + _{𝑅1}
The value of R1 should be less than 500kΩ, so that the input current on FB pin can reduce its
influence on the accuracy of the output voltage. The C_FF capacitor is used to compensate the gain
of the loop for improved stability and the value of the capacitor is usually 4.7pF to 22pF, but it is
optional.
Capacitor Selection
The input capacitor reduces the surge current drawn from the input and switching noise from the
device. The input capacitor impedance at the switching frequency shall be less than input source
impedance to prevent high frequency switching current passing to the input. Ceramic capacitors
with X5R or X7R dielectrics are highly recommended because of their low ESR and small
temperature coefficients. For most applications, a 4.7µF capacitor is sufficient.
The AV_IN is separate from the PV_IN in the chip. A C_A capacitor can be used to decouple alone. The
AV_IN can also be directly connected to the positive electrode of the C_IN to decouple.
The output capacitor keeps output voltage ripple small and ensures regulation loop stable. The
output capacitor impedance shall be low at the switching frequency. Ceramic capacitor with X5R
or X7R dielectrics are recommended. For most applications, a 10µF capacitor is sufficient. For
smaller output voltage ripple, you can choose a bigger output capacitor.
Exposed Metal on the Bottom of the Package
The UM3502QA utilizes the lead frame as part of the electrical circuit. The lead frame offers
many advantages in thermal performance, in reduced electrical lead resistance and in overall foot
print. However, it does require some special considerations.
As part of the package assembly process, lead frame construction requires that for mechanical
support, some of the lead-frame metal be exposed at the point where wire-bond or internal
passives are attached. This results in several small pads being exposed on the bottom of the
package.
The “grayed-out” area in Figure 1 represents the area that should be clear of any metal (traces,
vias, or planes) on the top layer of the PCB.
1
Keep Out Area on
the Top Layer of
the PCB
Figure 1. Exposed Metal of the Package
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http://www.union-ic.com Rev.01 Nov.2015
9/13