UM809_15 Datasheet, PDF (6/14 Pages) Union Semiconductor, Inc. – 3-Pin Microprocessor Reset Circuits

UM809/810
Detailed Description
A microprocessor’s (µP’s) reset input starts the µP in a known state. The UM809/810 asserts reset
to prevent code-execution errors during power-up, power-down, or brownout conditions. They
assert a reset signal whenever the V_CC supply voltage declines below a preset threshold, keeping it
asserted for at least 140ms after V_CC has risen above the reset threshold. The UM809/810 has a
push-pull output stage.
Applications Information
V_CC Transient Rejection
In addition to issuing a reset to the µP during power-up, power-down, and brownout conditions,
the UM809/810 is relatively immune to short-duration negative-going V_CC transients (glitches).
Figure 9 shows typical transient duration vs. reset comparator overdrive, for which the
UM809/810 do not generate a reset pulse. The graph was generated using a negative-going pulse
applied to V_CC, starting 0.5V above the actual reset threshold and ending below it by the
magnitude indicated (reset comparator overdrive). The graph indicates the maximum pulse width
a negative-going V_CC transient can have without causing a reset pulse. As the magnitude of the
transient increases (goes farther below the reset threshold), the maximum allowable pulse width
decreases. Typically, for the UM8_L and UM8_M, a V_CC transient that goes 100mV below the
reset threshold and lasts 20µs or less will not cause a reset pulse. A 0.1µF bypass capacitor
mounted as close as possible to the V_CC pin provides additional transient immunity.
V_CC
400
T_A=+25^oC
320
V_TH
240
Overdrive
160
Duration
80
0
1
UM8XXL/M/J
UM8XXR/S/T
10
100
1000
RESET COMPARATOR OVERDRIVE (mV)
Figure 9. Maximum Transient Duration vs Overdrive for Glitch Rejection at 25°C
Output Signal Integrity during Power-Down
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When V_CC falls below 1V, the UM809 RESET output no longer sinks cur_{_}r_{_}e_{__}n_{__}t_{_}—_{____}i_{_}t_{_} becomes an
open circuit. Therefore, high-impedance CMOS logic inputs connected to RESET can drift to
undetermined voltages. This presents no problem in most applications since m_{_}o_{__}s_{__}t_{__}µ_{___}P_{___}and other
circuitry is inoperative with V_CC below 1V. Howe_{__}v_{__}e_{_}r_{_},_{___}i_{_}n_{___} applications where RESET must be
valid down to 0V, adding a pull-down resistor to RESET causes any stray leakage currents to
_____________
flow to ground, holding RESET low (Figure 10). R1’s value is not critical; 100kΩ is large
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http://www.union-ic.com Rev.06 Apr.2015
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