UM3157_14 Datasheet, PDF (4/8 Pages) Union Semiconductor, Inc. – Low-Voltage SPDT Analog Switch

UM3157
Electrical Characteristics (Continued)
Symbol
Parameter
Test Conditions
Vcc(V)
Limits (–40 to 85 °C)
Temp
Unit
Min Typ Max
AC Electrical Characteristics
t_PHL
t_PLH
tPZL
tPZH
tPLZ
tPHZ
tD
QINJ
OIRR
Propagation Delay
Bus to Bus (Note 9)
VI = OPEN
1.65 to1.95
2.3 to 2.7
Full
3.0 to 3.6
4.5 to 5.5
1.2
0.8 ns
0.3
Output Enable Time
Turn On Time
(A to Bn)
VI = 2×VCC for tPZL
VI = 0 V for tPZH
1.65 to1.95
7.0
2.3 to 2.7
3.0 to 3.6
Full
3.5
2.5
4.5 to 5.5
1.7
24
14
7.6
ns
5.7
Output Disable Time
Turn Off Time
(A Port to B Port)
VI = 2×VCC for tPLZ
VI = 0 V for tPHZ
1.65 to1.95
3.0
2.3 to 2.7
3.0 to 3.6
Full
2.0
1.5
4.5 to 5.5
0.8
13
7.5
5.3
ns
3.8
1.65 to1.95
0.5
Break Before Make Time
(Note 8)
2.3 to 2.7
3.0 to 3.6
Full
0.5
0.5
ns
4.5 to 5.5
0.5
Charge Injection
(Note 8)
CL = 0.1 nF,
VGEN = 0 V RGEN = 0Ω
5.0
3.3
Room
7.0
3.0
pC
Off Isolation (Note 10)
RL=50Ω, f = 10 MHz
1.65 to 5.5 Room
-57
dB
Xtalk
Crosstalk
RL=50Ω, f = 10 MHz
1.65 to 5.5 Room
-54
dB
BW
-3 dB Bandwidth
RL=50Ω
1.65 to 5.5 Room
250
MHz
THD
Total Harmonic Distortion
(Note8)
RL=600Ω
0.5VP-P
f=600Hz to 20kHz
5.0
Room
0.011
%
Capacitance
CIN
IN Pin Input Capacitance
(Note11)
VCC = 0V
2.3
pF
CIO-B
B Port Off Capacitance
(Note11)
VCC =5.0V
6.5
pF
CIOA-ON
A Port Capacitance when
Switch is Enabled (Note11)
VCC =5.0V
18.5
pF
Note 3: Measured by the voltage drop between A and B pins at the indicated current through the switch. On
Resistance is determined by the lower of the voltages on the two (A or B Ports).
Note 4: Parameter is characterized but not tested in production.
Note 5: ΔR_ON =︱R_{ON (B0)} − R_ON(B1) ︱measured at identical V_CC, temperature and voltage levels.
Note 6: Flatness is defined as the difference between the maximum and minimum value of On Resistance
over the specified range of conditions.
Note 7: Guaranteed by design.
Note 8: Guaranteed by design.
Note 9: This parameter is guaranteed by design but not tested. The bus switch contributes no propagation
delay other than the RC delay of the On Resistance of the switch and the 50 pF load capacitance,
when driven by an ideal voltage source (zero output impedance).
Note 10: Off Isolation = 20 log10 [V_A/V_Bn].
Note 11: T_A = +25, f = 1 MHz, Capacitance is characterized but not tested in production.
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