UM3487E Datasheet, PDF (10/14 Pages) Union Semiconductor, Inc. – ±15kV ESD-Protected, Fail-Safe, Hot-Swappable Auto Polarity Reversal RS-485 Transceivers

UM3487E
Detail Description
Polarity Reversal Function
With large node count RS485 network, it is common for some cable data lines to be wired
backwards during installation. When this happens, the node is unable to communicate over, he
must then rewire the connector, which is time consuming.
The UM3487E simplifies this task by including an automatic polarity reversal function inside.
Upon UM3487E power up, when DE=/RE=logic low, and RO keeps logic low over a predefined
time T_S (i.e T_S=200ms in UM3487E), the chip reverse its bus pins polarity, so B become
non-inverting, and A become inverting. Otherwise, the chip operates like any standard RS485
transceiver, and the bus pins have their normal polarity definition of A as non inverting and B as
inverting.
Union Semi’s unique automatic polarity reversal function is superior to that found on competing
devices, because the receiver’s full fail safe function is maintained, even when the RX polarity is
reversed.
Fail-Safe and Hot-Swap
The UM3487E guarantees a logic high receiver output when the receiver inputs are shorted or
open, or when they are connected to a terminated transmission line with all drivers disabled. This
is done by setting the receiver input threshold between -50mV and -200mV. If the differential
receiver input voltage V_ID is greater than or equal to -50mV, RO id logic high. If V_ID is less than
or equal to -200mV, RO is logic low. In the case of a terminated bus with all transmitters disabled,
the receiver’s differential input voltage is pulled to 0V by the termination. With the receiver
threshold of UM3487E, this results in logic high with a 50mV minimum noise margin, and this
-50mV to -200mV threshold complies with the ±200mV EIA/TIA-485 standard.
When circuit boards with RS485 transceiver are inserted into a hot or powered backplane,
differential disturbances to the data bus cab lead to data errors. Upon initial circuit board insertion,
the microprocessor undergoes its own power-up sequence. During this period, the processor/s
logic output drivers are high impedance and unable to driver the DE and /RE inputs of these
devices to a defined logic level. Leakage currents up to ±10μA from the high impedance state of
processor’s logic drivers could cause standard CMOS enable inputs of a transceiver to drift to an
incorrect logic level. Additionally, parasitic circuit board capacitance could cause coupling of V_CC
or GND to the enable inputs. Without the hot-swap capability, these facts could improperly enable
the transceiver’s driver or receiver.
When VCC rises, an internal pull down circuit holds DE low and /RE high. After the initial power
up sequence, the pull down/pull up circuit becomes transparent, resetting the hot-swap tolerable
input. This hot-swap input circuit enhances UM3487E’s performance in harsh environment
application.
±15kV ESD Protection
All pins on UM3487E device include ESD protection structures, and the family incorporates
advanced structures which allow the RS-485 pins (L1, L2) to survive ESD events up to ±15kV.
The RS-485 pins are particularly vulnerable to ESD damage because they typically connect to an
exposed port on the exterior of the finished product. The ESD structures withstand high ESD in all
states: normal operation, shutdown, and powered down. After an ESD event, circuits keep
working without latch up. The ESD protection can be tested in various ways and with reference to
the ground pin. The L1, L2 are characterized for protection to the following limits: ±15kV using
the Human Body Model and IEC61000-4-2, Air-Gap Discharge, and ±8kV Contact Discharge.
The logic pins (RO, /RE, DE, DI) are characterized for protection to the following limits: ±2kV
using the Human Body Model.
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http://www.union-ic.com Rev.02 Jan.2014
10/14