CHT4660-QAG_15 Datasheet, PDF (16/18 Pages) United Monolithic Semiconductors – DC-16GHz Attenuator

CHT4660-QAG
DC-16GHz Attenuator
Definition of the Sij reference planes
The reference planes used for Sij measurements given
above are symmetrical from the symmetrical axis of the
package (see drawing beside). The input and output
reference planes are located at 2.65mm offset (input
wise and output wise respectively) from this axis. Then,
the given Sij parameters incorporate the land pattern of
the evaluation motherboard recommended at the page
18.
Recommended package footprint
Refer to the application note AN0017 available at http://www.ums-gaas.com for package foot
print recommendations.
SMD mounting procedure
The SMD leadless package has been designed for high volume surface mount PCB
assembly process. The dimensions and footprint required for the PCB (motherboard) are
given in the drawings above.
For the mounting process standard techniques involving solder paste and a suitable reflow
process can be used. For further details, see application note AN0017.
Recommended ESD management
Refer to the application note AN0020 available at http://www.ums-gaas.com for ESD
sensitivity and handling recommendations for the UMS package products.
Recommended environmental management
Refer to the application note AN0019 available at http://www.ums-gaas.com for
environmental data on UMS package products.
Ref : DSCHT4660QAG0211- 30 Jul 2010
16/18
Specifications subject to change without notice
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