UM3758 Datasheet, PDF (7/18 Pages) UMC Corporation – TRi-STATE ProgrammaBle Encoder/Decoder

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Functional Description
General
The operating mode of the UM3756 series is controlled
by the MODE pin. When the ‘MODE’ pin is connected to
VDO the circuit will automatically switch to encoder
mode, then ‘TX/RX OUT’ pin acts as data out pin and
‘RX INP” pin act as an idle pin. When ‘MODE’ pin is
connected to Vss the circuit will switch to decoder
mode, then ‘TX/RX OUT” pin will switch to LOW if
comparison is OK, otherwise this pin will keep HIGH,
and “RX/INP’ receives waveform from detect circuit.
Encoder Mode
The encoder mode is selected by connecting “MODE
pin to Voo.
The transmit sequence is initiated by the power con-
nection and continuously transmits till power down.
Esch transmitted address bit is encoded into address
pulses (see Fig. 1). A logic zero is encoded as two
c o n s e c u t i v e l o n g pulses, a logic one as two con-
secutive short pulses and an open as a long pulse
followed by a short pulse. Esch transmitted data bit
is encoded into logic Zero or one and the data pulse
is the Same as the address pulse (see Fig. l), ie.,
the state of data pin is either one or Zero. The data
is one when connected to VDO or open and Zero when
connected to Vss.
The UM3756160A samples the 18 bit tri-state address
a n d encodes this parallel address data for trans-
mitting. These 16 address pins may ,Se in either of
three states (0, 1, open) allowing 3 = 367,420,469
possible combinations then $e UM3758120A provides
12-bit address and allows 3 = 531,441 possible com-
binations.
The UM37561 06A/B and UM375&064A/B provide address
bi and data bits, as described in Table 1.
Part
Number
Address
Bits
Address
Combinations
Data
Bits
Data
Combinations
UM37561 06A/
10
59,049
8
256
B/AM/BM
UM3756-064A/
a
6,561
4
16
B/AM/BM
Decoder Mode
Table 1
The decoder mode is selected by connecting “MODE” pin
(ex. UM375&106A/B) are assumed to be address bi.
to vss.
If the address bits match the address bits from
The decoder receives the serial data from the detect
detect circuit, the next eight data bits are stored
circuit and outputs the comparison result or data, if
and matched to the last valid data stored. When the
it is valid. The received data may inolude two types
second word with data is received, the address bis
- _{without data and with data.}
must match again, and if it does, the data bits are
checked against the previous stored data biis. If
For decoder without data ICs, such as UM375616OA and
the two words (eight bits data each) of data match,
UM3756120A the address word is examined bit by bit as
the data is transferred to the output data pins (Dl,
received; if two successive address words match the
D2 to DE!). If the decoder is momentary type, the data
address bis of Decoder, the “TX/RX OUT” pin will
pins will latch the data till the ‘TX/RX O U T ’ p i n
switch to LOW and t-wo successive unmatched address
switches to HIGH; for latch decoder, the data pins
words will cause ‘TX/RX OUT” pin to return to HIGH
will latch the data till the next valid data appears
(see Fig. 3-l).
(see Fig. 3-2). Although the address bits .are tri-
state (0, 1, open), the data information must be
For decoder with data IC, such as UM375&106A/B and
either one or Zero. An open state will be decoded as
UM375&064A/B, the address word with data word are
a logic one. The above table (Table 1) also describes ,, ._ ___
..
examined bit by bi as received. The first 10 bits
these (decoder with data).
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