UM3750_1 Datasheet, PDF (2/5 Pages) UMC Corporation – Programmable Encoder/Decoder

Block Diagram
R.C.INPUT - - - - - - -
urn3750
CPCLK
RID
I
I
L ^COMPARATOR
ERROR
CLR
MXCLKR
MXD
WD
7
i
STATE
CONTROLLER
TIM0
VLD
INIT
64ms/128ms
TIMER
I
VALID 4
COUNTER
Al-Al2
T/R OUT
Block Diagram Description
CPCLK CLK of Comparator
WXCLKR: CLK of Multiplexer when in Receiver mode
WXCLKT CLK of Multiplexer when in Transmitter mode
MXD:
Output data of Multiplexer (one of Al, A2 ....
A12)
RID
Sampled data by Sampling CKT
VLD.
“Valid” signal. It is used to trigger Valid 4
Counter and reset 64ms/128ms Timer
CLR:
ERROR:
TIMO :
T/R OUT:
INIT:
WD:
TXO:
PXO:
Clear signal of Comparator
Error signal from Comparator
TIMER time-out signal (64ms or 128ms)
Transmit/Receiver output pin
Reset signal of Valid 4 Counter
Word detected signal
Transmitter output
Receiver output
2-4