NDS332P Datasheet, PDF (1/3 Pages) Fairchild Semiconductor – P-Channel Logic Level Enhancement Mode Field Effect Transistor

SMD Type
Product specification
NDS332P
General Description
These P-Channel logic level enhancement mode power field
effect transistors are produced using Fairchild's proprietary, high
cell density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance. These
devices are particularly suited for low voltage applications such as
notebook computer power management, portable electronics,
and other battery powered circuits where fast high-side
switching, and low in-line power loss are needed in a very small
outline surface mount package.
Features
-1 A, -20 V, R_DS(ON) = 0.41 Ω @ V_GS= -2.7 V
R_DS(ON) = 0.3 Ω @ V_GS = -4.5 V.
Very low level gate drive requirements allowing direct
operation in 3V circuits. V_GS(th) < 1.0V.
Proprietary package design using copper lead frame for
superior thermal and electrical capabilities.
High density cell design for extremely low R_DS(ON).
Exceptional on-resistance and maximum DC current
capability.
Compact industry standard SOT-23 surface Mount
package.
________________________________________________________________________________
D
G
S
Asolute Maximum Ratings T_A = 25°C unless otherwise noted
Symbol Parameter
V_DSS
Drain-Source Voltage
V_GSS
Gate-Source Voltage - Continuous
I_D
Drain Current - Continuous
- Pulsed
(Note 1a)
P_D
Maximum Power Dissipation
(Note 1a)
(Note 1b)
T_J,T_STG Operating and Storage Temperature Range
THERMAL CHARACTERISTICS
R_θJA
Thermal Resistance, Junction-to-Ambient (Note 1a)
R_θJC
Thermal Resistance, Junction-to-Case (Note 1)
NDS332P
-20
±8
-1
-10
0.5
0.46
-55 to 150
250
75
Units
V
V
A
W
°C
°C/W
°C/W
http://www.twtysemi.com
[e-mail]
4008-318-123
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