FDV302P Datasheet, PDF (1/2 Pages) Fairchild Semiconductor – Digital FET, P-Channel

SMD Type
Product specification
FDV302P
Digital FET, P-Channel
General Description
This P-Channel logic level enhancement mode field effect
transistor is produced using Fairchild's proprietary, high cell
density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance. This
device has been designed especially for low voltage
applications as a replacement for digital transistors. Since
bias resistors are not required, this one P-channel FET can
replace several digital transistors with different bias resistors
such as the DTCx and DCDx series.
SOT-23
Mark:302
SuperSOT^TM-6
SuperSOT^TM-8
Features
-25 V, -0.12 A continuous, -0.5 A Peak.
R_DS(ON) = 13 Ω @ V_GS= -2.7 V
R_DS(ON) = 10 Ω @ V_GS = -4.5 V.
Very low level gate drive requirements allowing direct
operation in 3V circuits. V_GS(th) < 1.5V.
Gate-Source Zener for ESD ruggedness.
>6kV Human Body Model
Compact industry standard SOT-23 surface mount
package.
Replace many PNP digital transistors (DTCx and DCDx)
with one DMOS FET.
SO-8
SOT-223
SOIC-16
D
Absolute Maximum Ratings T_A = 25^oC unless otherwise noted
Symbol Parameter
V_DSS
Drain-Source Voltage
V_GSS
Gate-Source Voltage
I_D
Drain Current
- Continuous
- Pulsed
P_D
T_J,T_STG
ESD
Maximum Power Dissipation
Operating and Storage Temperature Range
Electrostatic Discharge Rating MIL-STD-883D
Human Body Model (100pf / 1500 Ohm)
THERMAL CHARACTERISTICS
R_θJA
Thermal Resistance, Junction-to-Ambient
http://www.twtysemi.com
[e-mail]
G
S
FDV302P
-25
-8
-0.12
-0.5
0.35
-55 to 150
6.0
357
Units
V
V
A
W
°C
kV
°C/W
4008-318-123
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