TS823_09 Datasheet, PDF (3/8 Pages) Taiwan Semiconductor Company, Ltd – Microprocessor Supervisory Circuit with Watchdog Timer & Manual Reset

TS823/824/825 Series
Microprocessor Supervisory Circuit
with Watchdog Timer & Manual Reset
Application Information
The TS823/824/825 are designed to interface with the reset input of a microprocessor and to prevent CPU execution
errors due to power up, power down, and other power supply errors. The TS823/824 also monitor the CPU health by
checking for signal transitions form the CPU at the WDI input.
Reset Output
Active low reset outputs are denoted as RESET, Active high reset output are denoted as (RESET),
A reset will be asserted if any of three things happen:
1. Vdd drops below the threshold (Vth)
2. The MR pin is pulled low.
3. The WDI pin does not detect a transition within the Watch Dog interval (TWD)
The reset will remain asserted for the prescribed reset interval after:
1. Vdd rises above the threshold (Vth)
2. MR goes high
3. The Watch Dog timer have timed out causing the reset to assert.
Manual Reset Input
The TS823 and TS825 feature a manual reset feature (MR). A logic low on the MR pin asserts a reset. The reset
remains asserted a long as the MR pin remains low. After the MR pin transitions to a high state the reset remains
asserted for the prescribed reset interval (TD2). The MR pin is internally pulled up to Vdd by a 100KΩ resistor. It is
internally de-bounced to reject switching transients.
The MR pin is ESD protected by diodes connected to Vdd and Gnd. So the MR pin should never be driven higher than
Vdd or lower than Gnd.
Watchdog Input
The TS823 and TS824 are equipped with a watchdog input (WDI). If the microprocessor does not produce a valid logic
edge at the watchdog input (WDI) within the prescribed watchdog interval (TWD) then a reset asserts. The reset
remains asserted for the required reset interval (TD2). Ata the end of the reset interval the reset is deasserted and the
watchdog interval timer starts again from zero.
If the watchdog input is left unconnected or is connected to a tri-stated buffer the watchdog function is disabled. As
soon as the WDI input is driven either low or high the watchdog function resumes with the watchdog timer set to zero.
Watchdog Input Current
The watchdog input pin (WDI) typically sources/sinks 8uA when driven high or low. So from a power dissipation point
of view the duty cycle of the waveform at WDI is unimportant. When the WDI pin is floating or tri-stated the power
supply current fall to less than 3uA.
Glitch Rejection
The TS823/824/825 family will reject negative going transients on the Vdd line to some extent. The smaller the
duration of the transient the larger its amplitude may be without triggering a reset. The “Glitch Rejection” chart in the
graphs section of this datasheet shows the relation between glitch amplitude and allowable glitch duration to avoid
unintended resets.
Accurate Output State at Low Vdd
With Vdd voltage on the order of the MOS transistor threshold (<1V) the outputs of the TS823/824/825 may become
undefined. For parts with active low output RESET a resistor placed between RESET and Gnd on the order of 100KΩ
will ensure that the RESET output stays low when Vdd is lower than the threshold voltage of the part. In a like manner
a resistor on the order of 100KΩ when placed between (RESET) and Vdd will ensure parts with active high output
(RESET) will remain high when Vdd is lower than the threshold voltage of the parts.
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Version: C07