TSM2N7002ED Datasheet, PDF (1/5 Pages) Taiwan Semiconductor Company, Ltd – 50V Dual N-Channel Enhancement Mode MOSFET

TSM2N7002ED
50V Dual N-Channel Enhancement Mode MOSFET
Pin assignment:
1. Source (2)
2. Gate (2)
3. Drain (1)
6. Drain (2)
5. Gate (1)
4. Source (1)
V_DS = 50V
R_{DS (on)}, Vgs @ 10V, Ids @ 250mA = 3Ω
R_{DS (on)}, Vgs @ 5V, Ids @ 50mA = 4Ω
Features
Dual N-channel in package.
Advanced trench process technology
High density cell design for ultra low on-resistance
High input impedance
High speed switching
No minority carrier storage time
CMOS logic compatible input
No secondary breakdown
Compact and low profile SOT-363 package
Ordering Information
Part No.
Packing
Package
TSM2N7002EDCU6 T & R (3kpcs/Rell) SOT-363
Block Diagram
Absolute Maximum Rating (Ta = 25^oC unless otherwise noted)
Parameter
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current
Pulsed Drain Current
Maximum Power Dissipation
Ta = 25 ^oC
Ta = 75 ^oC
Operating Junction Temperature
Operating Junction and Storage Temperature Range
Thermal Performance
Symbol
V_DS
V_GS
I_D
I_DM
P_D
T_J
T_J, T_STG
Parameter
Lead Temperature (1/8” from case)
Junction to Ambient Thermal Resistance (PCB mounted)
Note: Surface mounted on FR4 board t<=5sec.
Symbol
T_L
Rθja
Limit
50
± 20
250
1.0
200
150
+150
- 55 to +150
Limit
5
625
Unit
V
V
mA
A
mW
o_C
o_C
Unit
S
o_C/W
TSM2N7002ED
1-5
2004/12 rev. B