CY7B952_11 Datasheet, PDF (1/16 Pages) Cypress Semiconductor – SST™ SONET/SDH Serial Transceiver

CY7B952
SST™ SONET/SDH Serial Transceiver
SST™ SONET/SDH Serial Transceiver
Features
■ OC-3 Compliant with Bellcore and CCITT (ITU) specifications
on:
❐ Jitter Generation (<0.01 UI)
❐ Jitter Transfer (<130 kHz)
❐ Jitter Tolerance
■ SONET/SDH and ATM Compliant
■ Compatible with IGT WAC013, IGT WAC413, and PMC-Sierra
PM5343
■ Clock and data recovery from 51.84- or 155.52-MHz
datastream
■ 155.52-MHz clock multiplication from 19.44-MHz source
■ 51.84-MHz clock multiplication from 6.48-MHz source
■ 1% frequency agility
■ Line Receiver Inputs: No external buffering required
■ Differential output buffering
■ 100K ECL compatible I/O
■ No output clock “drift” without data transitions
■ Link Status Indication
■ Loop-back testing
■ Single +5 V supply
■ 24-pin SOIC
■ Compatible with fiber-optic modules, coaxial cable, and twisted
pair media
■ Power-down options to minimize power or crosstalk
■ Low operating current: <70 mA
■ 0.8 BiCMOS
Functional Description
The SONET/SDH Serial Transceiver (SST) is used in
SONET/SDH and ATM applications to recover clock and data
information from a 155.52-MHz or 51.84-MHz NRZ or NRZI
serial data stream and to provide differential data buffering for
the Transmit side of the system.
Logic Block Diagram
LOOP(t)
MODE
FC+
FC–
RIN+
RIN–
CD
PLL
RECEIVE
TRANSMIT
RCLK+
RCLK–
RSER+
RSER–
LFI(t)
TOUT+
TOUT–
TSER+
TSER–
PLL
x8
TCLK+
TCLK–
REFCLK+
REFCLK–
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-02018 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 9, 2011
[+] Feedback