TQP3M9035_15 Datasheet, PDF (9/11 Pages) TriQuint Semiconductor – High-Linearity LNA Gain Block

Pin Configuration and Description
TQP3M9035
High-Linearity LNA Gain Block
Pin 1 Reference Mark
NC ¹
RF In ²
NC ³
NC ⁴
8 _NC
7 _{RF Out}
6 _{Shut Down}
5 _NC
Backside Paddle - RF/DC GND
Pin No.
2
Label
RF In
Description
RF Input pin. A DC Block is required.
6
Shut Down
A high voltage turns off the device. If the pin is not connected or is less than 1V, then
the device will operate under its normal operating condition.
7
RF Out /
DCBias
RF Output pin. DC bias will also need to be injected through a RF bias choke/inductor
for operation.
1, 3, 4, 5, 8
NC
No electrical connection. Provide grounded land pads for PCB mounting integrity.
Backside Paddle
RF/DC
GND
RF/DC ground. Use recommended via pattern to minimize inductance and thermal
resistance; see PCB Mounting Pattern for suggested footprint.
Evaluation Board PCB Information
TriQuint PCB 1084112 Material and Stack-up
50 ohm line dimensions: width = .031”, spacing = .035”
Datasheet: Rev I 12-05-14
© 2014 TriQuint
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Disclaimer: Subject to change without notice
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