TQ8105 Datasheet, PDF (8/19 Pages) TriQuint Semiconductor – SONET/SDH Transceivers

TQ8105/TQ8106
PRELIMINARY DATA SHEET
Functional Description (continued)
Enhanced Diagnostics
The TQ8105 and TQ8106 incorporate on-chip clock
diagnostics, allowing fast, efficient fault detection and
isolation at the systems level.
78 MHz or 19 MHz tristatable TTL data bus. The timing is
shown in Figures 6 through 8. See the previous “Framer”
description for bit alignment details. The TQ8106 can
recover both clock and data from a NRZ data stream,
whereas the TQ8105 requires NRZ data and a recovered
clock.
The LOR (Loss Of Reference) output goes high when the
reference clock is absent. Note that this signal is not
latched and is only high when the reference clock is
missing. A reference clock is required for the TQ8106
CDR to function correctly.
The NSOL (Loss-of-signal input, active low, PECL/ECL
level) input allows the receiver to force zeroes onto the
demux outputs. A TTL-level signal may also be used for
NSOL if the resistor network, shown in the applications
section of this data sheet, is used. NSOL is useful when a
Loss Of Signal occurs on the receive optics, and a
quieting of invalid data is desired. The receiver is clocked
from the transmit clock when NSOL is active, and the
output RXBC clock is obtained from the transmit portion
of the TQ8105/TQ8106. This ensures compatibility with
devices, such as the PMC-Sierra S/UNI-622 and STTX
components, which may contain dynamic registers that
lose contents if clocks are removed. NSOL forces the
CDR to lock on REFCLK, except when in slave mode.
The LOS (Loss Of Signal) output goes high whenever
128-bit periods occur without transitions on the data
input to the demux. CLRLOS forces LOS low.
The RLOCK (Receiver LOCK) output goes low whenever the
signal on RXCK or the recovered clock drifts more than
500 ppm from the reference frequency. This output returns
high whenever the frequency accuracy is within 100 ppm.
Mux
The TQ8105/TQ8106 multiplexer converts a 78 MHz or
19 MHz byte-wide bus to a serial NRZ PECL/ECL data
stream. The bytes are clocked into the device with the
TXBC byte clock output. The timing is shown in Figures
6 through 8. Note that the TXBC output can be adjusted
in 90-degree phase increments to accommodate
variations in interface requirements. See Table 3 for
settings on the PH0 and PH1 pins controlling this
function. Data may also be clocked into the TQ8105/
TQ8106 by a 77 MHz reference, oscillator-clock source,
provided the data is within the timing limits shown in the
timing diagram labelled “Reference Clock Based
Transmit Timing.” The TQ8105 and TQ8106 do not
require the transmit latch found on earlier TQ8101
reference designs and are backwards compatible with
designs that have the latch incorporated.
High-Speed I/O and TTL Interfaces
The TQ8105/06P will operate with either PECL or ECL
operation on the high-speed I/O. With a single +5V
supply, the part interfaces directly with TTL and PECL
(Positive Emitter Coupled Logic). By providing an
additional -5.2V supply, the device’s high-speed I/O
becomes ECL, instead of PECL. The TQ8105/06S is
designed only for PECL high-speed I/0 operation with a
single +5V supply. The power supply connections for
PECL and ECL are shown in Table 6B.
Demux
The TQ8105/TQ8106 demultiplexer converts an NRZ
PECL/ECL data input, at either 155 Mb/s or 622 Mb/s,
and its corresponding PECL/ECL clock into a byte-parallel
The TTL outputs (Vcc) may be connected to either +5V or
+3.3V supplies. True TTL may be obtained with the +5V
connection; clamped operation, when connected to +3.3V,
ensures that maximum Voh levels do not exceed +3.3V.
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