TQ1089 Datasheet, PDF (5/10 Pages) TriQuint Semiconductor – 11-Output Configurable Clock Buffer

TQ1089
AC Characteristics
(V_DD = +5 V + 5%, T_A = 0 °C to +70 °C)
Symbol
t _CPWH
t _CPWL
t _IR
Input Clock (REFCLK)
CLK pulse width HIGH
CLK pulse width LOW
Input rise time (0.8 V - 2.0V)
Test Conditions (Figure 3) ¹
Figure 4
Figure 4
Min Typ Max Unit
3
--- — ns
3
--- — ns
— — 2.0 ns
Symbol
t _OR,t _OF
t _PD1 ²
t _PD2 ²
t _SKEW1 ³
t _SKEW2 ³
t _SKEW3 ³
t _SKEW4 ³
t _CYC ⁴
t _JP ⁵
t _JR ⁵
t _SYNC ⁶
Output Clocks (Q0–Q10)
Test Conditions (Figure 3) ¹
Min Typ Max Unit
Rise/fall time (0.8 V – 2.0V)
Figure 4
350 — 1400 ps
CLK ↑ to FBIN ↑ (TQ1089-MC500)
Figure 4
–850 –350 +150 ps
CLK ↑ to FBIN ↑ (TQ1089-MC700)
Figure 4
–1050 –350 +350 ps
Rise–rise, fall–fall (within group)
Figure 5
— 60 150 ps
Rise–rise, fall–fall (group-to-group, aligned) Figure 6 (skew 2 takes into account skew 1) — 75 350 ps
Rise-rise, fall-fall (group-to-group, non-aligned) Figure 7 (skew 3 takes into account skews 1, 2) — — 650 ps
Rise–fall, fall–rise
Figure 8 (skew 4 takes into account skew 3) — — 1200 ps
Duty-cycle Variation
Figure 4
–1000 0 +1000 ps
Period-to-Period Jitter
Figure 4
— 80 200 ps
Random Jitter
Figure 4
— 190 400 ps
Synchronization Time
—
10 500 µs
Notes: 1. All measurements are tested with a REFCLK having a rise time of 0.5 ns (0.8 V to 2.0 V).
2. The PLL maintains alignment of CLK and FBIN at all times. This specification applies to the rising edge only because the input duty
cycle can vary while the output duty cycle is typically 50/50. The delay t_PD is measured at the 1.5 V level between CLK and FBIN.
3. Skew specifies the width of the window in which outputs switch, and is measured at 1.5 V.
4. This specification represents the deviation from 50/50 on the outputs.
5. Jitter specifications refer to peak-to-peak value. t_JR is the jitter on the output with respect to the reference clock.
t_JP is the jitter on the output with respect to the output’s previous rising edge.
6. t_SYNC is the time required for the PLL to synchronize; this assumes the presence of a CLK signal and
a connection from one of the outputs to FBIN.
Figure 3. AC Test Circuit
+5 V
R1
Z
R2
+5 V
R1
Z
R2
Notes:
R1 = 160 Ω
R2 = 71 Ω
Y+Z=X
Y
FBIN ^Q0
Q1
Q2
•
•
•
•
CLK Q10
50 Ω
X
•
•
•
•
+5 V
R1 _{+5 V}
R2 ^R1
R2
+5 V
R1
R2
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