TQM8M9077_15 Datasheet, PDF (3/8 Pages) TriQuint Semiconductor – 0.05 to 4 GHz Digital Variable Gain Amplifier

TQM8M9077
0.05 – 4 GHz Digital Variable Gain Amplifier
Serial Control Interface
The TQM8M9077 has a CMOS SPI^TM input compatible serial interface. This serial control interface converts the serial
data input stream to parallel output word. The input is 3-wire (CLK, LE and SID) SPI^TM input compatible. At power
up, the serial control interface resets the DSA to the minimum gain state. The 6-bit SID (Serial Input Data) word is
loaded into the register on rising edge of the CLK, MSB first. When LE is high, CLK is internally disabled.
Serial Control Timing Characteristics (Test conditions: VDD = +5 V, Temp.=25 °C)
Parameter
Condition
Min
Max
Clock Frequency
50% Duty Cycle
10
LE Setup Time, tLESUP
after last CLK rising edge
10
LE Pulse Width, tLEPW
30
SID set-up time, tSDSUP
before CLK rising edge
10
SID hold-time, tSDHLD
after CLK rising edge
10
LE Pulse Spacing tLE
LE to LE pulse spacing
630
Propagation Delay tPLO
LE to Parallel output valid
30
Units
MHz
ns
ns
ns
ns
ns
ns
Serial Control DC Logic Characteristics (Test conditions: VDD = +5 V, Temp.=25 °C)
Parameter
Condition
Min
Max
Units
Input Low State Voltage, VIL
0
0.8
V
Input High State Voltage, VIH Min value shown valid for VDD=+5 V only
2.1
VDD
V
Output High State Voltage, VOH On SOD pin
2.0
VDD
V
Output Low State Voltage, VOL On SOD pin
0
0.8
V
Input Current, IIH / IIL
On SID, LE and CLK pins
−10
+10
µA
SERIN Control Logic Truth Table
6-Bit Control Word
Gain Relative to
MSB
LSB Maximum Gain
D5 D4 D3 D2 D1 D0
11111 1
Maximum Gain
11111 0
−0.5 dB
11110 1
11101 1
11011 1
−1 dB
−2 dB
−4 dB
10111 1
−8 dB
01111 1
−16 dB
00000 0
−31.5 dB
Any combination of the possible 64 states will provide a
reduction in gain of approximately the sum of the bits
selected.
Timing Diagram
CLK is internally disabled when LE is high
D5-D0
MSB-LSB
D5-D0
MSB-LSB
LE
CLK
SID
tSDSUP
tSDHLD
tPLO
tLESUP
tLEPW
Datasheet Rev. F 10-20-14
© 2014 TriQuint
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