TQ6122 Datasheet, PDF (10/23 Pages) TriQuint Semiconductor – 1 Gigasample/sec, 8-bit Digital-to-Analog Converter

TQ6122
Circuit Description
The TQ6122 DAC is based on a current-steering archi-
tecture in which weighted currents are switched by an
array of differential-pair switches into either the V_OUT
or V_OUT output, depending on the state of the input data
and blanking bits. Essentially, the DAC is comprised of
six circuit blocks: the input buffer, the data multiplexer,
blanking logic, master/slave latch array with segment
encode logic, differential-pair switches, and the current
source array. (See figure on page 1.)
Input Buffers
The input buffers compare the ECL data and control
input signals with the ECLREF level, amplify the differ-
ence, and translate this signal to the logic levels used
within the IC. By default, the ECL reference is set by an
internal generator; however, for best performance and
maximum noise margin over temperature, power supply,
and device-to-device variations, the user should provide
an external level. For general-purpose applications, a
simple resistive divider between D_GND and V_TT will
suffice. For extreme environments or for maximum
performance, the ECLREF level should be slaved to the
centerpoint of the incoming data. Refer to the “Digital
Inputs and Terminations” discussion later in this
document for additional information.
Note that the data inputs are complemented to indicate
that an increasing input value results in the V_OUT level
moving more negative.
Data Multiplexer
The DAC makes provision for accepting data from
either of two sources: from a single 8-bit-wide word at
the full conversion rate, or from two 8-bit-wide half-
speed words which are multiplexed together inside the
DAC under the control of the SELA input. In use, the
SELA input is set HIGH to select the A-Word data and
LOW to select the B-Word. It is generally best to use
the A-Word input when operating the DAC unmultiplexed,
although the B-Word supports full-rate transfers.
Blanking Logic
A separate BLANK input is included to allow the DAC to
be used in video display applications. When asserted
LOW, the BLANK input has no effect on the operation of
the DAC, and the state of the input data words controls
the positions of the current switches. When BLANK is
asserted HIGH, however, all internal data bits and the
internal blanking bit are synchronously forced HIGH at
the next negative-going clock transition, causing the
V_OUT output to go to its most negative level. This level
is the sum of the normal level associated with an input
code of 11111111 plus the increment due to the
blanking current being steered away from the V_OUT
output to V_OUT. See Figure 4 (B).
In order to provide more latitude in the timing of the
BLANK signal, the BLANK input is sampled only when
the A-Word is selected. When the B-Word is selected,
the state of the BLANK input at the time the SELA
control line goes LOW is held stable until SELA again
goes HIGH. In situations where blanking is not used,
it is important that the BLANK input be tied to a solid
logic LOW to prevent accidental assertion of BLANK =
HIGH. Note also that when the DAC is used in the
unmultiplexed mode, the data should be brought in on
the A-Word inputs, since with SELA = LOW (as would
be the case for B-Word operation), a transient HIGH
level at the BLANK input would never be cleared and
the DAC would lock up.
The BLANK_DISABLE pin is normally tied to the V_AA
rail, allowing I_BLANK to flow to the differential-pair
switch and then to the selected output. For applications
which do not use blanking, however, the standing
offset in the V_OUT output due to the unswitched
10
For additional information and latest specifications, see our website: www.triquint.com