TQ2061 Datasheet, PDF (1/6 Pages) TriQuint Semiconductor – High-Frequency Clock Generator

TRIQUINT
S E M I C O N D U C T O R, I N C .
Figure 1. Pinout Diagram
11 10 9 8 7 6 5
TQ2061
High-Frequency
Clock Generator
VDD ₁₂
NC 13
TEST1 14
TEST2 15
NC 16
NC 17
GND 18
Phase
VCO
÷20
MUX
4 NC
3 NC
Control
MUX
2 NC
1 NC
28 NC
27 NC
26
19 20 21 22 23 24 25
TriQuint’s TQ2061 is a high-frequency clock generator. It utilizes a 25 MHz
to 35 MHz TTL input to generate a 500 MHz to 700 MHz PECL output. The
TQ2061 has a completely self-contained Phase-Locked Loop (PLL) running
at 500 MHz to 700 MHz. This stable PLL allows for a low period-to-period
output jitter of 70 ps (max), and enables tight duty cycle control of 55% to
45% (worst case).
The TQ2061 provides optional 200-ohm on-chip pull-down resistors which
are useful if the output is AC-coupled to the device being driven. In order
to use these resistors, pin 20 (PDR2) should be connected to pin 21 (QN),
and pin 23 (PDR1) should be connected to pin 22 (Q).
Features
• Output frequency range:
500 MHz to 700 MHz
• One differential PECL output:
600 mV (min) swing
• Common-mode voltage:
V_DD –1.2 V (max),
V_DD –1.6 V (min)
• Period-to-period output jitter:
25 ps peak-to-peak (typ)
70 ps peak-to-peak (max)
• Reference clock input:
25 MHz to 35 MHz TTL-level
crystal oscillator
• Self-contained loop filter
• Optional 200 Ω pull-down
resistors for AC-coupled outputs
• +5 V power supply
• 28-pin J-lead surface-mount
package
• Ideal for designs based on DEC
Alpha AXP^™ processors
Various test modes on the chip simplify debug and testing of systems by
slowing the clock output or by bypassing the PLL.
For additional information and latest specifications, see our website: www.triquint.com
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