TS3004 Datasheet, PDF (9/11 Pages) Touchstone Semiconductor Inc – A 1.55V to 5.25V, 1.9uA, 3.3us to 233s Silicon Timer

or example, if the instrument’s input probe
capacitance is 15pF and the desired effective load
capacitance at either or both FOUT and PWMOUT
terminals is to be ≤5p , then the value of C_EXT should
be ≤7.5p .
TS3004
TS3004 Start-up Time
As the TS3004 is powered up, its FOUT terminal
(and PWMOUT terminal, if enabled) is active once
the applied VDD is higher than 1.55V. Once the
applied VDD is higher than 1.55V, the master
oscillator achieves steady-state operation within 8ms.
Figure 2: 2 Weeks and 2 Days Counter Circuit
2 Weeks and 2 Days Counter Circuit with TS3004
The TS3004 can be configured into a 2 Weeks and 2
Days counter as shown in Figure 2. The circuit is
composed of a TS3004 timer and three dual
74VHC393 4-bit counters. The TS3004 divider inputs
are set to FDIV2:0 = 111. With an RS T of 4.32MΩ,
the FOUT period is approximately 1.4 minutes. The
complete circuit consumes approximately 11µA and
is powered with a single 3V CR2032 lithium button
cell battery. If a longer period is desired, a sixth
counter is available in the third 74VHC393.
Divide the PWMOUT Output Frequency by Two
with the TS3004
Using a single resistor and capacitor, the TS3004 can
be configured to a divide by two circuit as shown in
Figure 3. To achieve a divide by two function with the
TS3004, the pulse width of the PWMOUT output
must be at least a factor of 2 greater than the period
set at FOUT by resistor RSET. The CPWM capacitor
selected must meet this pulse width requirement and
can be calculated using Equation 2. In Figure 3, a
value of 4.32MΩ for RS T sets the O T output
period to 40µs. A CPWM capacitor of 265pF was
chosen, which sets the pulse width of PWMOUT to
TS3004DS r1p0
Figure 3: Configuring the TS3004 into a Divide by
Two Frequency Divider
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RTFDS