TS3006 Datasheet, PDF (3/9 Pages) Touchstone Semiconductor Inc – A 1.55V to 5.25V, 1.9uA, 9kHz to 300kHz Silicon Timer

TS3006
ELECTRICAL CHARACTERISTICS
VDD = 3V, VPWM_CNTRL= VDD, RSET = 4.32MΩ, RLOAD(FOUT) = Open Circuit, CLOAD(FOUT) = 0pF unless otherwise noted. Values are at TA = 25°C
unless otherwise noted. See Note 1.
PARAMETER
Supply Voltage
SYMBOL
VDD
CONDITIONS
MIN TYP MAX UNITS
1.55
5.25
V
Supply Current
IDD
-40°C ≤ TA ≤ 85°C
1.9 2.4
µA
2.7
FOUT Period
FOUT Period Line
Regulation
FOUT Duty cycle
FOUT Period
Temperature
Coefficient
UVLO Hysteresis
tFOUT
ΔtFOUT/V
ΔtFOUT/ΔT
VUVLO
1.55V ≤ VDD ≤ 5.25V
-40°C ≤ TA ≤ 85°C
(VDD=1.55V) – (VDD_SHUTDOWN VOLTAGE)
39 40.1 41.2
µs
38
42
0.17
%/V
49
51
%
0.02
%/°C
150
250 mV
FOUT Rise Time
tRISE
See Note 2, CL = 15pF
10
ns
FOUT Fall Time
tFALL
See Note 2, CL = 15pF
10
ns
FOUT Jitter
See Note 3
0.001
%
RSET Pin Voltage
V(RSET)
0.3
V
Maximum Oscillator
Frequency
High Level Output
Voltage, FOUT
Low Level Output
Voltage, FOUT
Fosc
VDD - VOH
VOL
RSET= 360K
IOH = 1mA
IOL = 1mA
300 kHz
160
mV
140
mV
Note 1: All devices are 100% production tested at TA = +25°C and are guaranteed by characterization for TA = TMIN to TMAX, as specified.
Note 2: Output rise and fall times are measured between the 10% and 90% of the VDD power-supply voltage levels. The specification is based
on lab bench characterization and is not tested in production.
Note 3: Timing jitter is the ratio of the peak-to-peak variation of the period to the mean of the period. The specification is based on lab bench
characterization and is not tested in production.
TS3006DS r1p0
Page 3
RTDFS