TMP86CS28FG Datasheet, PDF (94/230 Pages) Toshiba Semiconductor – 8 Bit Microcontroller

8. 16-Bit TimerCounter (TC10,TC11)
8.1 16-Bit TimerCounter 10
TMP86CS28FG
8.1.2 TimerCounter Control
The TimerCounter 10 is controlled by the TimerCounter 10 control register (TC10CR) and two 16-bit timer
registers (TC10DRA and TC10DRB).
Timer Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TC10DRA
(0011H, 0010H)
TC10DRAH (0011H)
(Initial value: 1111 1111 1111 1111)
TC10DRAL (0010H)
Read/Write
TC10DRB
(0013H, 0012H)
TC10DRBH (0013H)
(Initial value: 1111 1111 1111 1111)
TC10DRBL (0012H)
Read/Write (Write enabled only in the PPG output mode)
TimerCounter 10 Control Register
TC10CR
(0014H)
7
TFF10
6
ACAP10
MCAP10
METT10
MPPG10
5
4
TC10S
3
2
TC10CK
1
0
TC10M
Read/Write
(Initial value: 0000 0000)
TFF10
ACAP10
MCAP10
METT10
MPPG10
Timer F/F10 control
Auto capture control
Pulse width measure-
ment mode control
External trigger timer
mode control
PPG output control
TC10S TC10 start control
0: Clear
0:Auto-capture disable
0:Double edge capture
1: Set
1:Auto-capture enable
1:Single edge capture
0:Trigger start
1:Trigger start and stop
0:Continuous pulse generation
1:One-shot
Extrig-
Timer
Event
ger
00: Stop and counter clear
O
O
O
01: Command start
O
–
–
10: Rising edge start
(Ex-trigger/Pulse/PPG)
–
O
O
Rising edge count (Event)
Positive logic count (Window)
11: Falling edge start
(Ex-trigger/Pulse/PPG)
–
O
O
Falling edge count (Event)
Negative logic count (Window)
NORMAL1/2, IDLE1/2 mode
Win-
dow
O
–
O
O
DV7CK = 0
DV7CK = 1
TC10CK
TC10M
TC10 source clock select 00
[Hz]
01
fc/2¹¹
fc/2⁷
fs/2³
fc/2⁷
10
fc/2³
fc/2³
11
External clock (TC10 pin input)
TC10 operating mode
select
00: Timer/external trigger timer/event counter mode
01: Window mode
10: Pulse width measurement mode
11: PPG (Programmable pulse generate) output mode
R/W
R/W
Pulse PPG
O
O
–
O
O
O
R/W
O
O
Divider
SLOW,
SLEEP
mode
DV9 fs/2³
DV5
–
R/W
DV1
–
R/W
Note 1: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz]
Note 2: The timer register consists of two shift registers. A value set in the timer register becomes valid at the rising edge of the
first source clock pulse that occurs after the upper byte (TC10DRAH and TC10DRBH) is written. Therefore, write the
lower byte and the upper byte in this order (it is recommended to write the register with a 16-bit access instruction). Writing
only the lower byte (TC10DRAL and TC10DRBL) does not enable the setting of the timer register.
Note 3: To set the mode, source clock, PPG output control and timer F/F control, write to TC10CR1 during TC10S=00. Set the
timer F/F10 control until the first timer start after setting the PPG mode.
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