TMP88PH40MG Datasheet, PDF (84/158 Pages) Toshiba Semiconductor – 8 Bit Microcontroller

11. Motor Control Circuit (PMD: Programmable motor
driver)
TMP88PH40MG
Timer Circuit Registers [Addresses (PMD1)]
MTCRB
7
6
5
4
3
2
1
0
(01FA5H) DBOUT
–
TMOF
–
CLCP SWCP PDCCP
–
(Initial value: 0*0*0 000*)
0: Disable
7
DBOUT
Debug output
R/W
1: Enable (P67 for PMD1, P77 for PMD2)
0: No overflow
5
TMOF
Mode timer overflow
R
1: Overflowed
Capture mode timer by over- 0: Disable
3
CLCP
R/W
load protection
1: Enable
0: No operation
2
SWCP
Capture mode timer in software
W
1: Capture
Capture mode timer by position 0: Disable
1
PDCCP
R/W
detection
1: Enable
Note: Read-modify-write instructions, such as a bit manipulation instruction, cannot access the MTCRB because it contains a
write-only bit.
MTCRA
7
(01FA4H)
6
TMCK
5
4
3
2
1
0
RBTM3 RBCL SWRES RBPDC TMEN (Initial value: 0000 0000)
000: fc/2³ (400 ns at 20 MHz)
010: fc/2⁴ (800 ns at 20 MHz)
100: fc/2⁵ (1.6 µs at 20 MHz)
7, 6, 5 TMCK
Select clock
110: fc/2⁶ (3.2 µs at 20 MHz)
001: fc/2⁷ (6.4 µs at 20 MHz)
011: Reserved
R/W
101: Reserved
111: Reserved
4
RBTM3
0: Disable
Reset mode timer from Timer 3
1: Enable
3
RBCL
Reset mode timer by overload 0: Disable
protection
1: Enable
0: No operation
2
SWRES
Reset mode timer in software
W
1: Reset
1
RBPDC
Reset mode timer by position
detection
0: Disable
1: Enable
R/W
0
TMEN
Enable/disable mode timer
0: Disable
1: Enable timer start
Note 1: When changing MTCRA<TMCK> setting, keep the MTCRA<TMEN> bit reset to “0” (disable mode timer).
Note 2: Read-modify-write instructions, such as a bit manipulation instruction, cannot access the MTCRA because it contains a
write-only bit.
MCAP
FEDCBA 9 8 7 6 5 4 3 2 1 0
(01FA7H, 01FA6H)
(Initial value: 0000 0000 0000
DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ₀₀₀₀₎
MCAP
Mode capture
Position detection interval
R
CMP1
FEDCBA 9 8 7 6 5 4 3 2 1 0
(01FA9H, 01FA8H)
(Initial value: 0000 0000 0000
DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ₀₀₀₀₎
CMP2
FEDCBA 9 8 7 6 5 4 3 2 1 0
(01FABH, 01FAAH)
(Initial value: 0000 0000 0000
DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ₀₀₀₀₎
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