TMPR4951B Datasheet, PDF (83/256 Pages) Toshiba Semiconductor – 64-Bit TX System RISC TX49 Family

Chapter 4 Memory Management System
4. Memory Management System
The TX4951B provides a full-featured memory management unit (MMU) which uses an on-chip translation
look aside buffer (TLB) to translate virtual addresses into physical addresses.
4.1 Address Space Overview
The TX4951B physical address space is 4 Gbytes using a 32-bit address. The virtual address is either 64 or
32 bits wide depending on whether the processor is operating in 64- or 32-bit mode. In 32-bit mode,
addresses are 32-bits wide and the maximum user process size is 2 Gbytes (2³¹). In 64-bit mode, addresses
are 64-bit wide and the maximum user process is 1 Tbytes (2⁴⁰). The virtual address is extended with an
Address Space Identifier (ASID) to reduce the frequency of TLB flushing when switching context. The size
of the ASID field is 8 bits. The ASID is contained in the CP0 EntryHi register.
4.1.1 Virtual Address Space
The processor virtual address can be either 32 or 64 bits wide, depending on whether the processor is
operating in 32-bit or 64-bit mode.
• In 32-bit mode, addresses are 32 bits wide.
The maximum user process size is 2 Gbytes (2³¹).
• In 64-bit mode, addresses are 64 bits wide.
The maximum user process size is 1 Tbytes (2⁴⁰).
Figure 4.1.1 shows the translation of a virtual address into a physical address.
1. Virtual address (VA) represented by the virtual
G
page number (VPN) is compared with tag in
the TLB.
ASID
Virtual address
VPN
Offset
2. If there is a match, the page frame number
(PFN) representing the upper bits of the
physical address (PA) is output from the
TLB.
3. The Offset, which does not pass through the
TLB, is then concatenated to the PFN.
G
TLB
ASID
VPN
PFN
PFN
TLB
Entry
Offset
Physical address
Figure 4.1.1 Overview of a Virtual-to-Physical Address Translation
As shown in Figure 4.1.2 and Figure 4.1.3, the virtual address is extended with an 8-bit address space
identifier (ASID), which reduces the frequency of TLB flushing when switching contexts. This 8-bit
ASID is in the CP0 EntryHi register, described later in this chapter. The Global bit (G) is in the
EntryLo0 and EntryLo1 registers, described later in this chapter.
4-1